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Result 1 to 20 of 57 total

A faster hierarchical balanced bipartitioner for VLSI floorplans using monotone staircase cuts. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 327-336 (2012).
1
Workload driven power domain partitioning. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 147-155 (2012).
2
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 69-78 (2012).
3
A methodology for generation of performance models for the sizing of analog high-level topologies. (English)
VLSI Des. 2011, Article ID 475952, 17 p. (2011).
4
A methodology for generation of performance models for the sizing of analog high-level topologies (English)
VLSI Design 2011 (2011).
5
Verification of register transfer level low power transformations (English)
ISVLSI, 313-314 (2011).
6
Equivalence checking of array-intensive programs (English)
ISVLSI, 156-161 (2011).
7
An improved greedy construction of minimum connected dominating sets in wireless networks (English)
WCNC, 790-795 (2011).
8
Verification of datapath and controller generation phase in high-level synthesis of digital circuits. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 3, 479-492 (2010).
9
An automated high-level topology generation procedure for continuous-time $ΣΔ$ modulator. (English)
Integr., VLSI J. 43, No. 3, 289-304 (2010).
10
Minimum connected dominating set using a collaborative cover heuristic for ad hoc sensor networks (English)
IEEE Trans. Parallel Distrib. Syst. 21, No. 3, 292-302 (2010).
11
Data-flow driven equivalence checking for verification of code motion techniques (English)
ISVLSI, 428-433 (2010).
12
A BDD-based design of an area-power efficient asynchronous adder (English)
ISVLSI, 29-34 (2010).
13
A BDD-based approach to design power-aware on-line detectors for digital circuits (English)
SoCC, 343-346 (2010).
14
Efficient clusterhead rotation {\it via} domatic partition in self-organizing sensor networks. (English)
Wireless Commun. Mob. Comput. 9, No. 8, 1040-1058 (2009).
15
Rotation of CDS via connected domatic partition in ad hoc sensor networks (English)
IEEE Trans. Mob. Comput. 8, No. 4, 488-499 (2009).
16
Location updates of mobile node in wireless sensor networks (English)
MSN, 311-318 (2009).
17
Systematic methodology for high-level performance modeling of analog systems (English)
VLSI Design, 361-366 (2009).
18
A fast exploration procedure for analog high-level specification translation. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27, No. 8, 1493-1497 (2008).
19
An equivalence-checking method for scheduling verification in high-level synthesis. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27, No. 3, 556-569 (2008).
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Result 1 to 20 of 57 total