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Result 1 to 19 of 19 total

Object detection and segmentation from joint embedding of parts and pixels. (English)
ICCV, 2142-2149(2011)
WorldCat.org
1
Contour Detection and Hierarchical Image Segmentation. (English)
IEEE Trans. Pattern Anal. Mach. Intell.IEEE Trans. Pattern Anal. Mach. Intell. 33, N0. 5, 898-916(2011)
WorldCat.org
2
Occlusion boundary detection and figure/ground assignment from optical flow. (English)
CVPR, 2233-2240(2011)
WorldCat.org
3
Simultaneous segmentation and figure/ground organization using angular embedding. (English)
Daniilidis, Kostas (ed.) et al., Computer vision ‒ ECCV 2010. 11th European conference on computer vision, Heraklion, Crete, Greece, September 5‒11, 2010. Proceedings, Part II. Berlin: Springer (ISBN 978-3-642-15551-2/pbk). Lecture Notes in Computer Science 6312, 450-464 (2010).
WorldCat.org
4
FPGA Implementations of the Round Two SHA-3 Candidates. (English)
FPL, 400-407(2010)
WorldCat.org
5
FPGA implementation and analysis of random delay insertion countermeasure against DPA. (English)
FPT, 201-208(2008)
WorldCat.org
6
High-speed $&$ low area hardware architectures of the whirlpool hash function. (English)
J. VLSI Signal Process. 47, No. 1, 47-57 (2007).
WorldCat.org
7
High-Radix Systolic Modular Multiplication on Reconfigurable Hardware. (English)
FPT, 13-18(2005)
WorldCat.org
8
Recognition by probabilistic hypothesis construction. (English)
Pajdla, Tomáš (ed.) et al., Computer vision ‒ ECCV 2004. 8th European conference on computer vision, Prague, Czech Republic, May 11‒14, 2004. Proceedings, Part I. Berlin: Springer (ISBN 3-540-21984-6/pbk). Lecture Notes in Computer Science 3021, 55-68 (2004).
WorldCat.org
9
FPGA Montgomery Multiplier Architectures - A Comparison. (English)
FCCM, 279-282(2004)
WorldCat.org
10
FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p). (English)
ISCAS (3), 509-512(2004)
WorldCat.org
11
Rijndael FPGA implementations utilising look-up tables. (English)
J. VLSI Signal Process. Syst. Signal Image Video Technol. 34, No.3, 261-275 (2003).
Classification: E.4 E.3
WorldCat.org
13
Very High Speed 17 Gbps SHACAL Encryption Architecture. (English)
FPL, 111-120(2003)
WorldCat.org
14
A high-speed, low latency RSA decryption silicon core. (English)
ISCAS (4), 133-136(2003)
WorldCat.org
15
Efficient single-chip implementation of SHA-384 and SHA-512. (English)
FPT, 311-314(2002)
WorldCat.org
16
High performance single-chip FPGA Rijndael algorithm implementations. (English)
Koç, Çetin K. (ed.) et al., Cryptographic hardware and embedded systems - CHES 2001. 3rd international workshop, Paris, France, May 14-16, 2001. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2162, 65-76 (2001).
WorldCat.org
17
Single-chip FPGA implementation of the advanced encryption standard algorithm. (English)
Brebner, Gordon (ed.) et al., Field-programmable logic and applications. 11th international conference, FPL 2001, Belfast, Northern Ireland, GB, August 27-29, 2001. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2147, 152-161 (2001).
WorldCat.org
18
Nucleic acid binding and intracellular localization of unr, a protein with five cold shock domains. (English)
Nucleic Acids Res. 22, No. 13, 2643-2650 (1994).
WorldCat.org
19
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Result 1 to 19 of 19 total

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