Result 1 to 12 of 12 total
Power/performance exploration of single-core and multi-core processor approaches for biomedical signal processing. (English)
Ayala, José L. (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 21st international workshop, PATMOS 2011, Madrid, Spain, September 26‒29, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24153-6/pbk). Lecture Notes in Computer Science 6951, 102-111 (2011).
1
Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 1, 124-134 (2011).
2
Power/performance exploration of single-core and multi-core processor approaches for biomedical signal processing (English)
PATMOS, 102-111 (2011).
3
Design space exploration for 3D-stacked drams (English)
DATE, 389-394 (2011).
4
A fully-synthesizable single-cycle interconnection network for shared-L1 processor clusters (English)
DATE, 491-496 (2011).
5
A new physical routing approach for robust bundled signaling on noc links (English)
ACM Great Lakes Symposium on VLSI, 3-8 (2010).
6
An efficient distributed memory interface for many-core platform with 3D stacked DRAM (English)
DATE, 99-104 (2010).
7
3D nocs - unifying inter \& intra chip communication (English)
ISCAS, 3337-3340 (2010).
8
Synthesis of low-overhead configurable source routing tables for network interfaces (English)
DATE, 262-267 (2009).
9
Developing mesochronous synchronizers to enable 3D nocs (English)
DATE, 1414-1419 (2008).
10
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links (English)
ICCAD, 598-602 (2008).
11
Area and power modeling for networks-on-chip with layout awareness (English)
VLSI Design 2007 (2007).
12
Result 1 to 12 of 12 total
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