Result 1 to 14 of 14 total
A method for designing high-radix multiplier-based processing units for multimedia applications. (English)
IEEE Trans. Circuits Syst. Video Technol. 15, No. 5, 716-725 (2005).
1
A radix-8 multiplier design and its extension for efficient implementation of imaging algorithms (English)
SAMOS, 324-333 (2005).
2
Multiple-symbol parallel decoding for variable length codes. (English)
IEEE Trans. VLSI Syst. 12, No. 7, 676-685 (2004).
3
A family of accelerators for matrix-vector arithmetics based on high-radix multiplier structures (English)
SAMOS, 118-127 (2004).
4
High-level energy estimation for ARM-based socs (English)
SAMOS, 168-177 (2004).
5
Memory bandwidth requirements of tile-based rendering (English)
SAMOS, 323-332 (2004).
6
Scene management models and overlap tests for tile-based rendering (English)
DSD, 424-431 (2004).
7
Efficient hardware for antialiasing coverage mask generation (English)
Computer Graphics International, 257-264 (2004).
8
GRAAL - A development framework for embedded graphics accelerators (English)
DATE, 1366-1367 (2004).
9
Low cost and latency embedded 3D graphics reciprocation (English)
ISCAS (2), 905-908 (2004).
10
Graalbench: a 3D graphics benchmark suite for mobile phones (English)
LCTES, 1-9 (2004).
11
FPGA-based variable length decoders (English)
VLSI-SOC, 437-441 (2003).
12
Overview of research efforts on media ISA extensions and their usage in video coding. (English)
IEEE Trans. Circuits Syst. Video Technol. 12, No. 8, 660- (2002).
13
Parallel multiple-symbol variable-length decoding (English)
ICCD, 126-131 (2002).
14
Result 1 to 14 of 14 total
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