Result 1 to 20 of 133 total
Fast graph-based instruction selection for multi-output instructions. (English)
Softw., Pract. Exper. 41, No. 6, 717-736 (2011).
1
Multiprocessor systems on chip. Design space exploration. (English)
New York, NY: Springer (ISBN 978-1-4419-8152-3/hbk; 978-1-4419-8153-0/ebook). xix, 189~p. EUR~99.95/net; SFR~143.50; \sterling~90.00; \$~129.00 (2011).
2
A retargetable framework for compiler/architecture co-development (English)
Design Autom. for Emb. Sys. 15, No. 3-4, 311-342 (2011).
3
Optimized communication architecture of mpsocs with a hardware scheduler: A system-level analysis (English)
IJERTCS 2, No. 3, 1-20 (2011).
4
Fast graph-based instruction selection for multi-output instructions (English)
Softw., Pract. Exper. 41, No. 6, 717-736 (2011).
5
Trends in embedded software synthesis (English)
ICSAMOS, 347-354 (2011).
6
Virtual manycore platforms: moving towards 100+ processor cores (English)
DATE, 715-720 (2011).
7
Analytical and simulation-based design space exploration of software defined radios. (English)
Int. J. Parallel Program. 38, No. 3-4, 303-321 (2010).
8
Processor and system-on-chip simulation. (English)
Dordrecht: Springer (ISBN 978-1-4419-6174-7/hbk; 978-1-4419-6175-4/ebook). xiii, 345~p. EUR~129.95/net; SFR~165.00; \sterling~89.50 (2010).
9
Handbook of signal processing systems. Foreword by S. Y. Kung. (English)
New York, NY: Springer (ISBN 978-1-4419-6344-4/hbk; 978-1-4419-6345-1/ebook). xxxviii, 1083~p. EUR~189.95/net; SFR~286.50; \sterling~166.50; \$~249.00 (2010).
10
Automatic generation of memory interfaces for asips (English)
IJERTCS 1, No. 3, 1-23 (2010).
11
A scalable VLSI architecture for soft-input soft-output single tree-search sphere decoding (English)
IEEE Trans. on Circuits and Systems 57-II, No. 9, 706-710 (2010).
12
Mpsoc programming using the MAPS compiler (English)
ASP-DAC, 897-902 (2010).
14
Towards network centric development of embedded systems (English)
ICC, 1-6 (2010).
15
Trace-based KPN composability analysis for mapping simultaneous applications to mpsoc platforms (English)
DATE, 753-758 (2010).
16
Cool mpsoc programming (English)
DATE, 1488-1493 (2010).
17
Parsc: synchronous parallel systemc simulation on multi-core host architectures (English)
CODES+ISSS, 241-246 (2010).
18
A scalable VLSI architecture for soft-input soft-output depth-first sphere decoding. (English)
Comput. Res. Repos. 2009, Article No. 0910.3427 (2009).
19
A SIMD optimization framework for retargetable compilers. (English)
ACM Trans. Archit. Code Optim. 6, No. 1 (2009).
20
Result 1 to 20 of 133 total