Result 1 to 18 of 18 total
Design of multi-mode application-specific cores based on high-level synthesis. (English)
Integr., VLSI J. 45, No. 1, 9-21 (2012).
1
Design and implementation of a multi-core crypto-processor for software defined radios. (English)
Koch, Andreas (ed.) et al., Reconfigurable computing: architectures, tools and applications. 7th international symposium, ARC 2011, Belfast, UK, March 23‒25, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-19474-0/pbk). Lecture Notes in Computer Science 6578, 29-40 (2011).
2
Latency-sensitive high-level synthesis for multiple word-length DSP design (English)
EURASIP J. Adv. Sig. Proc. 2011 (2011).
3
Word-length aware DSP hardware design flow based on high-level synthesis (English)
Signal Processing Systems 62, No. 3, 341-357 (2011).
4
A reconfigurable multi-core cryptoprocessor for multi-channel communication systems (English)
IPDPS Workshops, 204-211 (2011).
5
Assertion support in high-level synthesis design flow (English)
FDL, 1-8 (2011).
6
Design and implementation of a multi-core crypto-processor for software defined radios (English)
ARC, 29-40 (2011).
7
Reducing and smoothing power consumption of ROM-based controller implementations (English)
SBCCI, 8-13 (2010).
8
A low-area filter bank design methodology for on-chip ADC testing (English)
ICECS, 718-721 (2010).
9
High-level synthesis for the design of FPGA-based signal processing systems (English)
ICSAMOS, 25-32 (2009).
10
Design and implementation of a reconfigurable decimation and channel selection filter for GSM and UMTS radio standards (English)
WCNC, 323-328 (2009).
11
Dynamic memory access management for high-performance DSP applications using high-level synthesis. (English)
IEEE Trans. VLSI Syst. 16, No. 11, 1454-1464 (2008).
12
Synthèse de haut niveau tenant compte de la dynamique des traitements. Analyse de la largeur des données d’applications du TDSI et gestion de cette information lors de la synthèse de haut niveau (English)
Technique et Science Informatiques 27, No. 9-10, 1129-1154 (2008).
13
A new orthogonal online digital calibration for time-interleaved analog-to-digital converters (English)
ISCAS, 576-579 (2008).
14
Bit-width optimizations for high-level synthesis of digital signal processing systems (English)
SiPS, 280-285 (2006).
15
Pipelined memory controllers for DSP applications handling unpredictable data accesses (English)
ISVLSI, 268-269 (2005).
16
Hardware virtual components compliant with communication system standards (English)
DSD, 88-95 (2005).
17
Reed-Solomon behavioral virtual component for communication systems (English)
ISCAS (4), 173-176 (2004).
18
Result 1 to 18 of 18 total
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