Low-complexity FFT/IFFT IP hardware macrocells for OFDM and MIMO-OFDM CMOS transceivers (English)
Microprocessors and Microsystems - Embedded Hardware Design 33, No. 3, 191-200 (2009).
1
Low-complexity link microarchitecture for mesochronous communication in networks-on-chip. (English)
IEEE Trans. Comput. 57, No. 09, 1196-1201 (2008).
2
Automatic synthesis of cost effective FFT/IFFT cores for VLSI OFDM systems (English)
IEICE Transactions 91-C, No. 4, 487-496 (2008).
3
Low-complexity link microarchitecture for mesochronous communication in networks-on-chip (English)
IEEE Trans. Computers 57, No. 9, 1196-1201 (2008).
4
Hardware/software FPGA-based network emulator for high-speed on-board communications (English)
DSD, 353-359 (2008).
5
Automatic generation of low-complexity FFT/IFFT cores for multi-band OFDM systems (English)
DSD, 361-368 (2007).
6
Low complexity LDPC code decoders for next generation standards (English)
DATE, 331-336 (2007).
7
High-throughput multi-rate decoding of structured low-density parity-check codes (English)
IEICE Transactions 88-A, No. 12, 3539-3547 (2005).
8
VLSI design of a high-throughput multi-rate decoder for structured LDPC codes (English)
DSD, 202-209 (2005).
9
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