Result 1 to 20 of 90 total
Designing smooth communication environment for telemedicine for general practitioner. (English)
Okumura, Manabu (ed.) et al., New frontiers in artificial intelligence. JSAI-isAI 2011 workshops, LENLS, JURISIN, ALSIP, MiMI, Takamatsu, Japan, December 1‒2, 2011. Revised selected papers. Berlin: Springer (ISBN 978-3-642-32089-7/pbk). Lecture Notes in Computer Science 7258. Lecture Notes in Artificial Intelligence, 253-263 (2012).
1
Vertical link on/off control methods for wireless 3-D NoCs. (English)
Herkersdorf, Andreas (ed.) et al., Architecture of computing systems ‒ ARCS 2012. 25th international conference, Munich, Germany, February 28‒March 2, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-28292-8/pbk). Lecture Notes in Computer Science 7179, 212-224 (2012).
2
A 60-ghz injection-locked frequency divider using multi-order {\it LC} oscillator topology for wide locking range (English)
IEICE Transactions 94-C, No. 6, 1049-1052 (2011).
3
A vertical bubble flow network using inductive-coupling for 3-D cmps (English)
NOCS, 49-56 (2011).
4
Thruchip interface (TCI) for 3D networks on chip (English)
VLSI-SoC, 238-241 (2011).
5
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator (English)
ESSCIRC, 471-474 (2011).
6
A 12Gb/s non-contact interface with coupled transmission lines (English)
ISSCC, 492-494 (2011).
7
$6W/25mm^{2}$ inductive power transfer for non-contact wafer-level testing (English)
ISSCC, 230-232 (2011).
8
A $2.7Gb/s/mm^{2} 0$.9pJ/b/chip 1coil/channel thruchip interface with coupled-resonator-based CDR for NAND flash memory stacking (English)
ISSCC, 490-492 (2011).
9
Modeling and experimental verification of misalignment tolerance in inductive-coupling inter-chip link for low-power 3-D system integration. (English)
IEEE Trans. VLSI Syst. 18, No. 8, 1238-1243 (2010).
10
Application of advanced grammatical evolution to function prediction problem. (English)
Adv. Eng. Softw. 41, No. 12, 1287-1294 (2010).
11
io-port 50111846 Chen, Yanfei;
Zhu, Xiaolei;
Tamura, Hirotaka;
Kibune, Masaya;
Tomita, Yasumoto;
Hamada, Takayuki;
Yoshioka, Masato;
Ishikawa, Kiyoshi;
Takayama, Takeshi;
Ogawa, Junji;
Tsukamoto, Sanroku;
Kuroda, Tadahiro
Split capacitor DAC mismatch calibration in successive approximation ADC (English)
IEICE Transactions 93-C, No. 3, 295-302 (2010).
12
A 4-gbps quasi-millimeter-wave transmitter in 65 nm CMOS and a fast carrier and symbol timing recovery scheme (English)
IEICE Transactions 93-C, No. 1, 120-127 (2010).
13
A dynamic offset control technique for comparator design in scaled CMOS technology (English)
IEICE Transactions 93-A, No. 12, 2456-2462 (2010).
14
A 9-bit 100-MS/s 1.46-mw tri-level SAR ADC in 65 nm CMOS (English)
IEICE Transactions 93-A, No. 12, 2600-2608 (2010).
15
Analysis of inductive coupling and design of rectifier circuit for inter-chip wireless power link (English)
IEICE Transactions 93-C, No. 2, 164-171 (2010).
16
47\% power reduction and 91\% area reduction in inductive-coupling programmable bus for NAND flash memory stacking (English)
IEEE Trans. on Circuits and Systems 57-I, No. 9, 2269-2278 (2010).
17
A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications (English)
CICC, 1-4 (2010).
18
A 60-ghz 1.65mW 25.9\% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS (English)
CICC, 1-4 (2010).
19
An 8Tb/s 1pJ/b $0.8mm^{2}/tb/s$ QDR inductive-coupling interface between 65nm CMOS GPU and $0.1μm$ DRAM (English)
ISSCC, 436-437 (2010).
20
Result 1 to 20 of 90 total
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