Result 1 to 17 of 17 total
Are you having fun yet? (English)
IEEE Design & Test of Computers 27, No. 6, 80 (2010).
1
An x86-64 core implemented in 32nm SOI CMOS (English)
ISSCC, 106-107 (2010).
2
Keeping hot chips cool: are IC thermal problems hot air? (English)
DAC, 634-635 (2008).
3
Multi-dimensional circuit and micro-architecture level optimization (English)
ISQED, 275-280 (2007).
4
Structured and tuned array generation (STAG) for high-performance random logic (English)
ACM Great Lakes Symposium on VLSI, 257-262 (2007).
5
Early power-aware design \& validation: myth or reality? (English)
DAC, 210-211 (2007).
6
Experimental measurement of a novel power gating structure with intermediate power saving mode (English)
ISLPED, 20-25 (2004).
7
Characterization of logic circuit techniques for high leakage CMOS technologies (English)
ACM Great Lakes Symposium on VLSI, 230-235 (2004).
8
io-port 05420485 Plouchart, Jean-Olivier;
Zamdmer, Noah;
Kim, Jonghae;
Sherony, Melanie;
Tan, Yue;
Ray, Asit;
Talbi, Mohamed;
Wagner, Lawrence F.;
Wu, Kun;
Lustig, Naftali E.;
Narasimha, Shreesh;
O’neil, Patricia;
Phan, Nghia;
Rohn, Michael;
Strom, James;
Friend, David M.;
Kosonocky, Stephen V.;
Knebel, Daniel R.;
Kim, Suhwan;
Jenkins, Keith A.;
Rivier, Michel M.
Application of an SOI $0.12-μm$ CMOS technology to socs with low-power and high-frequency circuits. (English)
IBM J. Res. Dev. 47, No. 5-6, 611-630 (2003).
9
io-port 05420400 Kosonocky, Stephen V.;
Bhavnagarwala, Azeez J.;
Chin, Kenneth;
Gristede, George;
Haen, Anne-Marie;
Hwang, Wei;
Ketchen, Mark B.;
Kim, Suhwan;
Knebel, Daniel R.;
Warren, Kevin W.;
Zyuban, Victor V.
Low-power circuits and technology for wireless digital systems. (English)
IBM J. Res. Dev. 47, No. 2-3, 283-298 (2003).
10
Understanding and minimizing ground bounce during mode transition of power gating structures (English)
ISLPED, 22-25 (2003).
11
Optimal supply and threshold scaling for subthreshold CMOS circuits (English)
ISVLSI, 7-14 (2002).
12
Low power integrated scan-retention mechanism (English)
ISLPED, 98-102 (2002).
13
Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design (English)
ISLPED, 263-266 (2001).
14
Enchanced multi-threshold (MTCMOS) circuits using variable well bias (English)
ISLPED, 165-169 (2001).
15
Interconnect-centric array architectures for minimum SRAM access time (English)
ICCD, 400-405 (2001).
16
Result 1 to 17 of 17 total
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