Result 1 to 20 of 31 total
An equivalent-time and clocked approach for continuous-time quantization (English)
ISCAS, 2529-2532 (2011).
1
Thin film joining for high-temperature performance of power semi-conductor devices (English)
Microelectronics Reliability 50, No. 2, 220-227 (2010).
2
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links (English)
DATE, 1755-1760 (2010).
3
Interconnect-aware pipeline synthesis for array-based architectures (English)
IEICE Transactions 92-A, No. 6, 1464-1475 (2009).
4
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation (English)
CICC, 701-704 (2009).
5
io-port 70452326 Niitsu, Kiichi;
Shimazaki, Yasuhisa;
Sugimori, Yasufumi;
Kohama, Yoshinori;
Kasuga, Kazutaka;
Nonomura, Itaru;
Saen, Makoto;
Komatsu, Shigenobu;
Osada, Kenichi;
Irie, Naohiko;
Hattori, Toshihiro;
Hasegawa, Atsushi;
Kuroda, Tadahiro
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM (English)
ISSCC, 480-481 (2009).
6
Signature-based testing for digitally-assisted adaptive equalizers in high-speed serial links (English)
European Test Symposium, 107-112 (2009).
7
A novel metric embedding optimal normalization mechanism for clustering of series data (English)
IEICE Transactions 91-D, No. 9, 2369-2371 (2008).
8
Using counterexample analysis to minimize the number of predicates for predicate abstraction. (English)
Namjoshi, Kedar S. (ed.) et al., Automated technology for verification and analysis. 5th international symposium, ATVA 2007 Tokyo, Japan, October 22‒25, 2007. Proceedings. Berlin: Springer (ISBN 978-3-540-75595-1/pbk). Lecture Notes in Computer Science 4762, 553-563 (2007).
9
Using counterexample analysis to minimize the number of predicates for predicate abstraction (English)
ATVA, 553-563 (2007).
10
Protocol transducer synthesis using divide and conquer approach (English)
ASP-DAC, 280-285 (2007).
11
Interconnect-aware pipeline synthesis for array based reconfigurable architectures (English)
IESS, 121-134 (2007).
12
The AMS extension to system level design language - specc (English)
IEICE Transactions 89-A, No. 12, 3397-3407 (2006).
13
Adaptive clock recovery method utilizing proportional-integral-derivative (PID) control for circuit emulation (English)
IEICE Transactions 89-B, No. 3, 690-695 (2006).
14
Synchronization verification in system-level design with ILP solvers (English)
IEICE Transactions 89-A, No. 12, 3387-3396 (2006).
15
Synchronization mechanism for timed/untimed mixed-signal system level design environment (English)
IEICE Transactions 89-A, No. 4, 1018-1026 (2006).
16
Functional characterization of gibberellin-regulated genes in Rice using microarray system (English)
Genomics, Proteomics & Bioinformatics 4, No. 3, 137-144 (2006).
17
An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme (English)
ISCAS (2006).
18
Low power and fault tolerant encoding methods for on-chip data transfer in practical applications (English)
IEICE Transactions 88-A, No. 12, 3282-3289 (2005).
19
Synchronization verification in system-level design with ILP solvers (English)
MEMOCODE, 121-130 (2005).
20
Result 1 to 20 of 31 total
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