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io-port 70390737 Kheterpal, V.; Rovner, Vyacheslav; Hersan, T. G.; Motiani, D.; Takegawa, Y.; Strojwas, Andrzej J.; Pileggi, Lawrence T.

Design methodology for IC manufacturability based on regular logic-bricks (English)

DAC, 353-358 (2005).

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io-port 70391347 Kheterpal, V.; Strojwas, Andrzej J.; Pileggi, Lawrence T.

Routing architecture exploration for regular fabrics (English)

DAC, 204-207 (2004).

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io-port 70690095 Koorapaty, Aneesh; Kheterpal, V.; Gopalakrishnan, Padmini; Fu, M.; Pileggi, Lawrence T.

Exploring logic block granularity for regular fabrics (English)

DATE, 468-473 (2004).

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io-port 70389412 Pileggi, Lawrence T.; Schmit, Herman; Strojwas, Andrzej J.; Gopalakrishnan, Padmini; Kheterpal, V.; Koorapaty, Aneesh; Patel, Chetan; Rovner, Vyacheslav; Tong, K. Y.

Exploring regular fabrics to optimize the performance-cost trade-off (English)

DAC, 782-787 (2003).

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io-port 70733156 Rajendran, Bipin; Kheterpal, Veerbhan; Das, Abhishek; Majumder, Jayanta; Mandal, Chittaranjan A.; Chakrabarti, P. P.

Timing analysis of tree-like RLC circuits (English)

ISCAS (4), 838-841 (2002).

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