Result 1 to 20 of 37 total
Microvisor: A runtime architecture for thermal management in chip multiprocessors. (English)
Stenström, Per (ed.), Transactions on High-Performance Embedded Architectures and Compilers IV. Berlin: Springer (ISBN 978-3-642-24567-1/pbk). Lecture Notes in Computer Science 6760. Journal Subline, 84-110 (2011).
1
Remote data checking using provable data possession. (English)
ACM Trans. Inf. Syst. Secur. 14, No. 1, 12 (2011).
2
Hardware/software codesign architecture for online testing in chip multiprocessors (English)
IEEE Trans. Dependable Sec. Comput. 8, No. 5, 714-727 (2011).
3
DCC: A dependable cache coherence multicore architecture (English)
Computer Architecture Letters 10, No. 1, 12-15 (2011).
4
Microvisor: A runtime architecture for thermal management in chip multiprocessors (English)
T. HiPEAC 4, 84-110 (2011).
5
Scalable, accurate multicore simulation in the 1000-core era (English)
ISPASS, 175-185 (2011).
6
Deadlock-free fine-grained thread migration (English)
NOCS, 33-40 (2011).
7
Brief announcement: distributed shared memory based on computation migration (English)
SPAA, 253-256 (2011).
8
Arcc: A case for an architecturally redundant cache-coherence architecture for large multicores (English)
ICCD, 411-418 (2011).
9
Thread relocation: A runtime architecture for tolerating hard errors in chip multiprocessors (English)
IEEE Trans. Computers 59, No. 5, 651-665 (2010).
10
A self-adaptive scheduler for asymmetric multi-cores (English)
ACM Great Lakes Symposium on VLSI, 397-400 (2010).
11
A model to exploit power-performance efficiency in superscalar processors via structure resizing (English)
ACM Great Lakes Symposium on VLSI, 215-220 (2010).
12
Open columns: a carbon dioxide (CO2) responsive architecture (English)
CHI Extended Abstracts, 4789-4792 (2010).
13
Predictive thermal management for chip multiprocessors using co-designed virtual machines. (English)
Seznec, André (ed.) et al., High performance embedded architectures and compilers. Fourth international conference, HiPEAC 2009, Paphos, Cyprus, January 25‒28, 2009. Proceedings. Berlin: Springer (ISBN 978-3-540-92989-5/pbk). Lecture Notes in Computer Science 5409, 293-307 (2009).
14
Minimal sufficient explanations for factored Markov decision processes (English)
ICAPS (2009).
15
io-port 70584740 Kim, Wonsoo;
Khan, O.;
Truong, Kien T.;
Choi, Soon-Hyeok;
Grant, Robert;
Wright, Hyrum K.;
Mandke, Ketan;
Daniels, Robert C.;
Jr., Robert W. Heath;
Nettles, Scott
An experimental evaluation of rate adaptation for multi-antenna systems (English)
INFOCOM, 2313-2321 (2009).
16
Improving yield and reliability of chip multiprocessors (English)
DATE, 490-495 (2009).
17
A self-adaptive system architecture to address transistor aging (English)
DATE, 81-86 (2009).
18
Hardware/software co-design architecture for thermal management of chip multiprocessors (English)
DATE, 952-957 (2009).
19
Predictive thermal management for chip multiprocessors using co-designed virtual machines (English)
HiPEAC, 293-307 (2009).
20
Result 1 to 20 of 37 total
Start
Contact
Print
General Help
