Result 1 to 20 of 156 total
A switch block for multi-context FPGAs based on floating-gate-MOS functional pass-gates using multiple/binary valued hybrid signals. (English)
J. Mult.-Val. Log. Soft Comput. 17, No. 5-6, 553-580 (2011).
1
Implementation of a low-power FPGA based on synchronous/asynchronous hybrid architecture (English)
IEICE Transactions 94-C, No. 10, 1669-1679 (2011).
2
Memory allocation for window-based image processing on multiple memory modules with simple addressing functions (English)
IEICE Transactions 94-A, No. 1, 342-351 (2011).
3
Adaptive group-based job scheduling for high performance and reliable volunteer computing (English)
JIP 19, 39-51 (2011).
4
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture (English)
ASP-DAC, 89-90 (2011).
5
High performance tag singulation for memory-less RFID systems (English)
ICC, 1-6 (2011).
6
Logic-in-control-architecture-based reconfigurable VLSI using multiple-valued differential-pair circuits (English)
IEICE Transactions 93-D, No. 8, 2126-2133 (2010).
7
An asynchronous FPGA based on LEDR/4-phase-dual-rail hybrid architecture (English)
IEICE Transactions 93-C, No. 8, 1338-1348 (2010).
8
Task allocation with algorithm transformation for reducing data-transfer bottlenecks in heterogeneous multi-core processors: A case study of HOG descriptor computation (English)
IEICE Transactions 93-A, No. 12, 2570-2580 (2010).
9
Group testing based detection of web service ddos attackers (English)
IEICE Transactions 93-B, No. 5, 1113-1121 (2010).
10
Foreword (English)
IEICE Transactions 93-D, No. 8, 2025 (2010).
11
A switch block architecture for multi-context fpgas based on a ferroelectric-capacitor functional pass-gate using multiple/binary valued hybrid signals (English)
IEICE Transactions 93-D, No. 8, 2134-2144 (2010).
12
Adaptive selection of intelligent processing modules and its applications (English)
IC-AI, 513-520 (2010).
13
An field-programmable VLSI based on synchronous/asynchronous hybrid architecture (English)
ERSA, 271-274 (2010).
14
Architecture of an FPGA-oriented heterogeneous multi-core processor with SIMD-accelerator cores (English)
ERSA, 179-186 (2010).
15
Mapping for a heterogeneous multi-core media processor considering the data transfer time (English)
ERSA, 281-284 (2010).
16
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions (English)
IEEE Congress on Evolutionary Computation, 1-8 (2010).
17
Low-power multiple-valued reconfigurable VLSI based on superposition of bit-serial data and current-source control signals (English)
ISMVL, 179-184 (2010).
18
Implementation of a partially reconfigurable multi-context FPGA based on asynchronous architecture (English)
IEICE Transactions 92-C, No. 4, 539-549 (2009).
19
Result 1 to 20 of 156 total
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