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io-port 02045426 Iwata, Masaya; Kajitani, Isamu; Liu, Yong; Kajihara, Nobuki; Higuchi, Tetsuya

Implementation of a gate-level evolvable hardware chip. (English)

Liu, Yong (ed.) et al., Evolvable systems: from biology to hardware. 4th international conference, ICES 2001, Tokyo, Japan, October 3‒5, 2001. Proceedings. Berlin: Springer (ISBN 3-540-42671-X). Lect. Notes Comput. Sci. 2210, 38-49 (2001).

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io-port 01849109 Yamauchi, Tsukasa; Nakaya, Shogo; Inuo, Takeshi; Kajihara, Nobuki

Arithmetic operation oriented reconfigurable chip: RHW. (English)

Brebner, Gordon (ed.) et al., Field-programmable logic and applications. 11th international conference, FPL 2001, Belfast, Northern Ireland, GB, August 27-29, 2001. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2147, 618-622 (2001).

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io-port 70067952 Yamauchi, Tsukasa; Nakaya, Shogo; Inuo, Takeshi; Kajihara, Nobuki

Arithmetic operation oriented reconfigurable chip: RHW (English)

FPL, 618-622 (2001).

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io-port 70790544 Iwata, Masaya; Kajitani, Isamu; Liu, Yong; Kajihara, Nobuki; Higuchi, Tetsuya

Implementation of a gate-level evolvable hardware chip (English)

ICES, 38-49 (2001).

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io-port 70511378 Yamauchi, Tsukasa; Nakaya, Shogo; Inuo, Takeshi; Kajihara, Nobuki

Mapping algorithms for a multi-bit data path processing reconfigurable chip RHW (English)

FCCM, 281-282 (2000).

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io-port 05451985 Higuchi, Tetsuya; Iwata, Masaya; Keymeulen, Didier; Sakanashi, Hidenori; Murakawa, Masahiro; Kajitani, Isamu; Takahashi, Eiichi; Toda, Kenji; Salami, Mehrdad; Kajihara, Nobuki; Otsu, Nobuyuki

Real-world applications of analog and digital evolvable hardware . (English)

IEEE Trans. Evol. Comput. 3, No. 3, 220-235 (1999).

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io-port 05104952 Murakawa, Masahiro; Yoshizawa, Shuji; Kajitani, Isamu; Yao, Xin; Kajihara, Nobuki; Iwata, Masaya; Higuchi, Tetsuya

The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing. (English)

IEEE Transactions on Computers 48, No.06, 628-639 (1999).

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io-port 01935442 Higuchi, Tetsuya; Kajihara, Nobuki

Evolvable hardware chips for industrial applications. (English)

Commun. ACM 42, No. 4, 60-66 (1999).

Classification: B.7.1 B.7.0 Reviewer: A. D. Booth (Sooke, B.C., Canada)

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io-port 50176579 Murakawa, Masahiro; Yoshizawa, Shuji; Kajitani, Isamu; Yao, Xin; Kajihara, Nobuki; Iwata, Masaya; Higuchi, Tetsuya

The GRD chip: genetic reconfiguration of dsps for neural network processing (English)

IEEE Trans. Computers 48, No. 6, 628-639 (1999).

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io-port 70986142 Kajitani, Isamu; Hoshino, Tsutomu; Kajihara, Nobuki; Iwata, Masaya; Higuchi, Tetsuya

An evolvable hardware chip and its application as a multi-function prosthetic hand controller (English)

AAAI/IAAI, 182-187 (1999).

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io-port 70790346 Kajitani, Isamu; Hoshino, Tsutomu; Nishikawa, Daisuke; Yokoi, Hiroshi; Nakaya, Shougo; Yamauchi, Tsukasa; Inuo, Takeshi; Kajihara, Nobuki; Iwata, Masaya; Keymeulen, Didier; Higuchi, Tetsuya

A gate-level EHW chip: implementing GA operations and reconfigurable hardware on a single LSI (English)

ICES, 1-12 (1998).

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io-port 70985939 Sakanashi, Hidenori; Salami, Mehrdad; Iwata, Masaya; Nakaya, Shogo; Yamauchi, Tsukasa; Inuo, Takeshi; Kajihara, Nobuki; Higuchi, Tetsuya

Evolvable hardware chip for high precision printer image compression (English)

AAAI/IAAI, 486-491 (1998).

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io-port 70939233 Yamauchi, Tsukasa; Nakaya, Shogo; Kajihara, Nobuki

SOP: an adaptive massively parallel computer and its control-data-flow based compiling method (English)

Parcella, 128-136 (1996).

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