Result 1 to 20 of 24 total
Transactional memories for multi-processor FPGA platforms (English)
Journal of Systems Architecture - Embedded Systems Design 57, No. 1, 160-168 (2011).
1
Scalable arbiters and multiplexers for on-FGPA interconnection networks (English)
FPL, 90-96 (2011).
2
An efficient sequential iterative matching algorithm for CIOQ switches (English)
ISCC, 558-563 (2011).
3
Efficient implementation of CIOQ switches with sequential iterative matching algorithms (English)
FPT, 433-436 (2010).
4
End-to-end congestion management for non-blocking multi-stage switching fabrics (English)
ANCS, 6 (2010).
5
Network processing in multi-core fpgas with integrated cache-network interface (English)
ReConFig, 328-333 (2010).
6
Design and performance evaluation of an adaptive FPGA for network applications (English)
Microelectronics Journal 40, No. 7, 1103-1110 (2009).
7
Impbench: A novel benchmark suite for biomedical, microelectronic implants (English)
ICSAMOS, 82-91 (2008).
8
Queue management in network processors. (English)
Comput. Res. Repos. 2007, Article No. 0710.4813 (2007).
9
Design space exploration of configuration manager for network processing applications (English)
ICSAMOS, 34-40 (2007).
10
A reconfigurable platform for multi-service edge routers (English)
SBCCI, 165-170 (2007).
11
Configurable transactional memory (English)
FCCM, 65-72 (2007).
12
High-performance switching based on buffered crossbar fabrics. (English)
Comput. Netw. 50, No. 13, 2271-2285 (2006).
13
High-performance switching based on buffered crossbar fabrics. (English)
Comput. Netw. 50, No. 13, 2271-2285 (2006).
14
A dynamically reconfigurable queue scheduler (English)
FPL, 1-4 (2006).
15
Performance evaluation of an adaptive FPGA for network applications (English)
IEEE International Workshop on Rapid System Prototyping, 54-62 (2006).
16
Analysis of a reconfigurable network processor (English)
IPDPS (2006).
17
Design of a web switch in a reconfigurable platform (English)
ANCS, 31-40 (2006).
18
A reconfigurable hardware based embedded scheduler for buffered crossbar switches (English)
FPGA, 143-149 (2006).
19
An open TCP/IP core for reconfigurable logic (English)
FCCM, 297-298 (2005).
20
Result 1 to 20 of 24 total
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