Result 1 to 20 of 77 total
High level simulation of SVP many-core systems. (English)
Parallel Process. Lett. 21, No. 4, 413-438 (2011).
1
Resource-agnostic programming for many-core microgrids. (English)
Guarracino, Mario R. (ed.) et al., Euro-Par 2010 parallel processing workshops. HeteroPar, HPCC, HiBB, CoreGrid, UCHPC, HPCF, PROPER, CCPI, VHPC. Ischia, Italy, August 31 ‒ September 3, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-21877-4/pbk). Lecture Notes in Computer Science 6586, 109-116 (2011).
2
A micro threading based concurrency model for parallel computing (English)
IPDPS Workshops, 1668-1674 (2011).
3
Mapping distributed S-net on the 48-core intel SCC processor (English)
MARC Symposium, 41-46 (2011).
4
Efficient memory copy operations on the 48-core intel SCC processor (English)
MARC Symposium, 13-18 (2011).
5
On the compilation of a language for general concurrent target architectures. (English)
Parallel Process. Lett. 20, No. 1, 51-69 (2010).
6
HPPC 2009 panel: Are many-core computer vendors on track? (English)
Lin, Hai-Xiang (ed.) et al., Euro-Par 2009 ‒ parallel processing workshops. HPPC, HeteroPAR, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25‒28, 2009. Revised selected papers. Berlin: Springer (ISBN 978-3-642-14121-8/pbk). Lecture Notes in Computer Science 6043, 9-15 (2010).
7
Towards scalable I/O on a many-core architecture (English)
ICSAMOS, 341-348 (2010).
8
Resource-agnostic programming for many-core microgrids (English)
Euro-Par Workshops, 109-116 (2010).
9
Building a concurrency and resource allocation model into a processor’s ISA. (English)
César, E. (ed.) et al., Euro-Par 2008 workshops ‒ parallel processing. VHPC 2008, UNICORE 2008, HPPC 2008, SGS 2008, PROPER 2008, ROIA 2008, and DPA 2008, Las Palmas de Gran Canaria, Spain, August 25‒26, 2008. Revised selected papers. Berlin: Springer (ISBN 978-3-642-00954-9/pbk). Lecture Notes in Computer Science 5415, 129-130 (2009).
10
Evaluating CMPs and their memory architecture. (English)
Berekovic, Mladen (ed.) et al., Architecture of computing systems ‒ ARCS 2009. 22nd international conference, Delft, The Netherlands, March 10‒13, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-00453-7/pbk). Lecture Notes in Computer Science 5455, 246-257 (2009).
11
The implementation of an SVP many-core processor and the evaluation of its memory architecture (English)
SIGARCH Computer Architecture News 37, No. 2, 38-45 (2009).
12
Implementation and evaluation of a microthread architecture (English)
Journal of Systems Architecture - Embedded Systems Design 55, No. 3, 149-161 (2009).
13
An implementation of the SANE virtual processor using POSIX threads (English)
Journal of Systems Architecture - Embedded Systems Design 55, No. 3, 162-169 (2009).
14
HPPC 2009 panel: are many-core computer vendors on track? (English)
Euro-Par Workshops, 9-15 (2009).
15
Evaluating cmps and their memory architecture (English)
ARCS, 246-257 (2009).
16
The verification of the on-chip COMA cache coherence protocol. (English)
Meseguer, José (ed.) et al., Algebraic methodology and software technology. 12th international conference, AMAST 2008, Urbana, IL, USA, July 28‒31, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-79979-5/pbk). Lecture Notes in Computer Science 5140, 413-429 (2008).
17
An architecture and protocol for the management of resources in ubiquitous and heterogeneous systems based on the SVP model of concurrency. (English)
Bereković, Mladen (ed.) et al., Embedded computer systems: Architectures, modeling, and simulation. 8th international workshop, SAMOS 2008, Samos, Greece, July 21‒24, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-70549-9/pbk). Lecture Notes in Computer Science 5114, 218-228 (2008).
18
Introduction to programming multicores. (English)
Bereković, Mladen (ed.) et al., Embedded computer systems: Architectures, modeling, and simulation. 8th international workshop, SAMOS 2008, Samos, Greece, July 21‒24, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-70549-9/pbk). Lecture Notes in Computer Science 5114, 207 (2008).
19
On-chip COMA cache-coherence protocol for microgrids of microthreaded cores. (English)
Bougé, Luc (ed.) et al., Euro-Par 2007 workshops: Parallel processing. HPPC 2007, UNICORE summit 2007, and VHPC 2007, Rennes, France, August 28‒31, 2007. Revised selected papers. Berlin: Springer (ISBN 978-3-540-78472-2/pbk). Lecture Notes in Computer Science 4854, 38-48 (2008).
20
Result 1 to 20 of 77 total
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