Result 1 to 20 of 40 total
Turbo product code decoder without interleaving resource: from parallelism exploration to high efficiency architecture (English)
Signal Processing Systems 64, No. 1, 17-29 (2011).
1
Area and throughput optimized ASIP for multi-standard turbo decoding (English)
International Symposium on Rapid System Prototyping, 79-84 (2011).
2
Hardware efficiency versus error probability in unreliable computation (English)
SiPS, 168-173 (2011).
3
A low complexity stopping criterion for reducing power consumption in turbo decoders (English)
DATE, 649-654 (2011).
4
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding (English)
DATE, 228-233 (2011).
5
Parallelism efficiency in convolutional turbo decoding. (English)
EURASIP J. Adv. Signal Process. 2010, Article ID 927920, 11 p. (2010).
6
Scaling of analog LDPC decoders in sub-100 nm CMOS processes. (English)
Integr., VLSI J. 43, No. 4, 365-377 (2010).
7
Parallelism efficiency in convolutional turbo decoding (English)
EURASIP J. Adv. Sig. Proc. 2010 (2010).
8
A new single-error correction scheme based on self-diagnosis residue number arithmetic (English)
DASIP, 27-33 (2010).
9
Rapid design and prototyping of universal soft demapper (English)
ISCAS, 3769-3772 (2010).
10
High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping. (English)
J. Signal Process. Syst. Signal Image Video Technol. 57, No. 3, 349-361 (2009).
11
ASIP-based universal demapper for multiwireless standards (English)
Embedded Systems Letters 1, No. 1, 9-13 (2009).
12
High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping (English)
Signal Processing Systems 57, No. 3, 349-361 (2009).
13
Rapid prototyping of ASIP-based flexible MMSE-IC linear equalizer (English)
IEEE International Workshop on Rapid System Prototyping, 130-133 (2009).
14
Flexible architectures for LDPC decoders based on network on chip paradigm (English)
DSD, 582-589 (2009).
15
ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applications (English)
DATE, 1620-1625 (2009).
16
Design of an iterative receiver for linearly precoded MIMO systems (English)
ISCAS, 597-600 (2009).
17
Decoding a family of dense codes using the sum-product algorithm (English)
ISCAS, 2685-2688 (2009).
18
From application to ASIP-based FPGA prototype: a case study on turbo decoding (English)
IEEE International Workshop on Rapid System Prototyping, 128-134 (2008).
19
A highly parallel turbo product code decoder without interleaving resource (English)
SiPS, 1-6 (2008).
20
Result 1 to 20 of 40 total
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