History


Please fill in your query. A complete syntax description you will find on the General Help page.
first | previous | 1 21 | next | last

Result 1 to 20 of 32 total

Stochastic multiple stream decoding of cortex codes (English)
IEEE Transactions on Signal Processing 59, No. 7, 3486-3491 (2011).
WorldCat.org
1
Turbo product code decoder without interleaving resource: from parallelism exploration to high efficiency architecture (English)
Signal Processing Systems 64, No. 1, 17-29 (2011).
WorldCat.org
2
Efficient iterative receiver for bit-interleaved coded modulation according to the DVB-T2 standard (English)
ICASSP, 3168-3171 (2011).
WorldCat.org
3
A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: design, implementation and FPGA prototyping (English)
SiPS, 55-60 (2011).
WorldCat.org
4
Hardware efficiency versus error probability in unreliable computation (English)
SiPS, 168-173 (2011).
WorldCat.org
5
Assertion support in high-level synthesis design flow (English)
FDL, 1-8 (2011).
WorldCat.org
6
Stochastic decoding of turbo codes (English)
IEEE Transactions on Signal Processing 58, No. 12, 6421-6425 (2010).
WorldCat.org
7
A new single-error correction scheme based on self-diagnosis residue number arithmetic (English)
DASIP, 27-33 (2010).
WorldCat.org
8
Design and implementation of a soft-decision decoder for cortex codes (English)
ICECS, 663-666 (2010).
WorldCat.org
9
High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping. (English)
J. Signal Process. Syst. Signal Image Video Technol. 57, No. 3, 349-361 (2009).
WorldCat.org
10
Turbo decoding of product codes using adaptive belief propagation (English)
IEEE Transactions on Communications 57, No. 10, 2864-2867 (2009).
WorldCat.org
11
High-throughput block turbo decoding: from full-parallel architecture to FPGA prototyping (English)
Signal Processing Systems 57, No. 3, 349-361 (2009).
WorldCat.org
12
Design of rotated QAM mapper/demapper for the DVB-T2 standard (English)
SiPS, 018-023 (2009).
WorldCat.org
13
FPGA prototyping approach for the validation of efficient iterative decoders in digital communication systems (English)
ERSA, 9-18 (2009).
WorldCat.org
14
Blind frame synchronization of product codes based on the adaptation of the parity check matrix (English)
ICC, 1-5 (2009).
WorldCat.org
15
Design of an iterative receiver for linearly precoded MIMO systems (English)
ISCAS, 597-600 (2009).
WorldCat.org
16
Reed-Solomon turbo product codes for optical communications: from code optimization to decoder design. (English)
EURASIP J. Wirel. Commun. Netw. 2008, Article ID 658042, 14 p. (2008).
WorldCat.org
17
Stochastic decoding of linear block codes with high-density parity-check matrices (English)
IEEE Transactions on Signal Processing 56, No. 11, 5733-5739 (2008).
WorldCat.org
18
Reed-Solomon turbo product codes for optical communications: from code optimization to decoder design (English)
EURASIP J. Wireless Comm. and Networking 2008 (2008).
WorldCat.org
19
A highly parallel turbo product code decoder without interleaving resource (English)
SiPS, 1-6 (2008).
WorldCat.org
20
first | previous | 1 21 | next | last

Result 1 to 20 of 32 total

Valid XHTML 1.0 Transitional Valid CSS!