Result 1 to 20 of 324 total
Optimizing sensor movement planning for energy efficiency. (English)
ACM Trans. Sens. Netw. 7, No. 4, 33 (2011).
1
Exploring performance-power tradeoffs in providing reliability for noc-based mpsocs (English)
ISQED, 495-501 (2011).
2
Morphcache: A reconfigurable adaptive multi-level cache hierarchy (English)
HPCA, 231-242 (2011).
3
io-port 05833381 Walton, N.A.;
Brenton, J.D.;
Caldas, C.;
Irwin, M.J.;
Akram, A.;
Gonzalez-Solares, E.;
Lewis, J.R.;
Maccallum, P.H.;
Morris, L.J.;
Rixon, G.T.
Pathgrid: a service-orientated architecture for microscopy image analysis. (English)
Philos. Trans. R. Soc. Lond., Ser. A, Math. Phys. Eng. Sci. 368, No. 1925, 3937-3952 (2010).
4
Total power optimization for combinational logic using genetic algorithms. (English)
J. Signal Process. Syst. Signal Image Video Technol. 58, No. 2, 145-160 (2010).
5
Technology scaling redirects Main memories: technical perspective. (English)
Commun. ACM 53, No. 7, 98 (2010).
6
On the effects of process variation in network-on-chip architectures (English)
IEEE Trans. Dependable Sec. Comput. 7, No. 3, 240-254 (2010).
7
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra (English)
IET Computers & Digital Techniques 4, No. 6, 484-498 (2010).
8
Total power optimization for combinational logic using genetic algorithms (English)
Signal Processing Systems 58, No. 2, 145-160 (2010).
9
Feasibility of automatically bootstrapping a persian wordnet (English)
LREC (2010).
10
Cache topology aware computation mapping for multicores (English)
PLDI, 74-85 (2010).
11
Shared caches in multicores: the good, the bad, and the ugly (English)
ISCA, 234 (2010).
12
Dynamic core partitioning for energy efficiency (English)
IPDPS Workshops, 1-8 (2010).
13
T-NUCA - a novel approach to non-uniform access latency cache architectures for 3D cmps (English)
IPDPS Workshops, 1-8 (2010).
14
Optimizing power and performance for reliable on-chip networks (English)
ASP-DAC, 431-436 (2010).
15
Compiler directed network-on-chip reliability enhancement for chip multiprocessors (English)
LCTES, 85-94 (2010).
16
Proceedings of wireless health 2010, WH 2010, San Diego, CA, USA, October 5-7, 2010 (English)
Wireless Health (2010).
17
Using data compression for increasing memory system utilization. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 28, No. 6, 901-914 (2009).
18
Compiler-assisted soft error detection under performance and energy constraints in embedded systems. (English)
ACM Trans Embed. Comput. Syst. 8, No. 4 (2009).
19
In-network caching for chip multiprocessors. (English)
Seznec, André (ed.) et al., High performance embedded architectures and compilers. Fourth international conference, HiPEAC 2009, Paphos, Cyprus, January 25‒28, 2009. Proceedings. Berlin: Springer (ISBN 978-3-540-92989-5/pbk). Lecture Notes in Computer Science 5409, 373-388 (2009).
20
Result 1 to 20 of 324 total
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