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io-port 05941136 Holsmark, Rickard; Kumar, Shashi; Palesi, Maurizio

A multi-level routing scheme and router architecture to support hierarchical routing in large network on chip platforms. (English)

Guarracino, Mario R. (ed.) et al., Euro-Par 2010 parallel processing workshops. HeteroPar, HPCC, HiBB, CoreGrid, UCHPC, HPCF, PROPER, CCPI, VHPC. Ischia, Italy, August 31 ‒ September 3, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-21877-4/pbk). Lecture Notes in Computer Science 6586, 153-161 (2011).

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io-port 70076607 Holsmark, Rickard; Kumar, Shashi; Palesi, Maurizio

A multi-level routing scheme and router architecture to support hierarchical routing in large network on chip platforms (English)

Euro-Par Workshops, 153-161 (2010).

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io-port 70197642 Palesi, Maurizio; Holsmark, Rickard; Wang, Xiaohang; Kumar, Shashi; Yang, Mei; Jiang, Yingtao; Catania, Vincenzo

An efficient technique for in-order packet delivery with adaptive routing algorithms in networks on chip (English)

DSD, 37-44 (2010).

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io-port 50152857 Palesi, Maurizio; Holsmark, Rickard; Kumar, Shashi; Catania, Vincenzo

Application specific routing algorithms for networks on chip (English)

IEEE Trans. Parallel Distrib. Syst. 20, No. 3, 316-330 (2009).

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io-port 70181405 Holsmark, Rickard; Kumar, Shashi; Palesi, Maurizio; Mejia, Andres

Hira: A methodology for deadlock free routing in hierarchical networks on chip (English)

NOCS, 2-11 (2009).

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io-port 50184842 Holsmark, Rickard; Palesi, Maurizio; Kumar, Shashi

Deadlock free routing algorithms for irregular mesh topology noc systems with rectangular regions (English)

Journal of Systems Architecture - Embedded Systems Design 54, No. 3-4, 427-440 (2008).

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io-port 70181435 Palesi, Maurizio; Longo, Giuseppe; Signorino, Salvatore; Holsmark, Rickard; Kumar, Shashi; Catania, Vincenzo

Design of bandwidth aware and congestion avoiding efficient routing algorithms for networks-on-chip platforms (English)

NOCS, 97-106 (2008).

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io-port 50321704 Holsmark, Rickard; Kumar, Shashi

Corrections to Chen and chiu’s fault tolerant routing algorithm for mesh networks (English)

J. Inf. Sci. Eng. 23, No. 6, 1649-1662 (2007).

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io-port 70269494 Palesi, Maurizio; Kumar, Shashi; Holsmark, Rickard; Catania, Vincenzo

Exploiting communication concurrency for efficient deadlock free routing in reconfigurable noc platforms (English)

IPDPS, 1-8 (2007).

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io-port 70019777 Palesi, Maurizio; Kumar, Shashi; Holsmark, Rickard

A method for router table compression for application specific routing in mesh topology noc architectures (English)

SAMOS, 373-384 (2006).

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io-port 70198441 Holsmark, Rickard; Palesi, Maurizio; Kumar, Shashi

Deadlock free routing algorithms for mesh topology noc systems with regions (English)

DSD, 696-703 (2006).

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io-port 71045133 Palesi, Maurizio; Holsmark, Rickard; Kumar, Shashi; Catania, Vincenzo

A methodology for design of application specific deadlock-free routing algorithms for noc systems (English)

CODES+ISSS, 142-147 (2006).

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io-port 02043466 Holsmark, Rickard; Högberg, Magnus; Kumar, Shashi

Modelling and evaluation of a network on chip architecture using SDL. (English)

Reed, Rick (ed.) et al., SDL 2003: System design. 11th international SDL forum, Stuttgart, Germany, July 1‒4, 2003. Proceedings. Berlin: Springer (ISBN 3-540-40539-9/pbk). Lect. Notes Comput. Sci. 2708, 166-182 (2003).

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io-port 70997873 Holsmark, Rickard; Högberg, Magnus; Kumar, Shashi

Modelling and evaluation of a network on chip architecture using SDL (English)

SDL Forum, 166-182 (2003).

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