Minimizing the number of delay buffers in the synchronization of pipelined systems. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 13, No. 12, 1441-1449 (1994).
1
An efficient implementation of singular value decomposition rotation transformations with CORDIC processors. (English)
J. Parallel Distrib. Comput. 17, No.4, 360-362 (1993).
2
Expanding the Range of Convergence of the CORDIC Algorithm. (English)
IEEE Transactions on Computers 40, No.01, 13-21 (1991).
3
Expanding the range of convergence of the CORDIC algorithm (English)
IEEE Trans. Computers 40, No. 1, 13-21 (1991).
4
Minimizing the number of delay buffers in the synchronization of pipelined systems (English)
DAC, 758-763 (1991).
5
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