Result 1 to 20 of 290 total
On-line residual life estimation with outlier judgement for condition based maintenance. (English)
Proceedings of the 42nd ISCIE international symposium on stochastic systems theory and its applications, Okayama, Japan, November 26‒27, 2010. Kyoto: The Institute of Systems, Control and Information Engineers (ISCIE) (ISBN 978-4-915740-52-7). 59-64 (2011).
1
Electromagnetic analysis enhancement with signal processing techniques (poster). (English)
Parampalli, Udaya (ed.) et al., Information security and privacy. 16th Australasian conference, ACISP 2011, Melbourne, Australia, July 11‒13, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-22496-6/pbk). Lecture Notes in Computer Science 6812, 456-461 (2011).
2
Buffer planning for IP placement using sliced-LFF. (English)
VLSI Des. 2011, Article ID 530851, 10 p. (2011).
3
Correlation power analysis based on switching glitch model. (English)
Chung, Yongwha (ed.) et al., Information security applications. 11th international workshop, WISA 2010, Jeju Island, Korea, August 24‒26, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-17954-9/pbk). Lecture Notes in Computer Science 6513, 191-205 (2011).
4
A novel depth-image based view synthesis scheme for multiview and 3DTV. (English)
Lee, Kuo-Tien (ed.) et al., Advances in multimedia modeling. 17th international multimedia modeling conference, MMM 2011, Taipei, Taiwan, January 5‒7, 2011. Proceedings, Part I. Berlin: Springer (ISBN 978-3-642-17831-3/pbk). Lecture Notes in Computer Science 6523, 161-170 (2011).
5
Buffer planning for IP placement using sliced-LFF (English)
VLSI Design 2011 (2011).
6
Watermarking for HDR image robust to tone mapping (English)
IEICE Transactions 94-A, No. 11, 2334-2341 (2011).
7
Optimized 2-D SAD tree architecture of integer motion estimation for H.264/AVC (English)
IEICE Transactions 94-C, No. 4, 411-418 (2011).
8
Cache based motion compensation architecture for quad-HD H.264/AVC video decoder (English)
IEICE Transactions 94-C, No. 4, 439-447 (2011).
9
A 530 mpixels/s intra prediction architecture for ultra high definition H.264/AVC encoder (English)
IEICE Transactions 94-C, No. 4, 419-427 (2011).
10
Greedy optimization algorithm for the power/ground network design to satisfy the voltage drop constraint (English)
IEICE Transactions 94-A, No. 4, 1082-1090 (2011).
11
Multiple region-of-interest based H.264 encoder with a detection architecture in macroblock level pipelining (English)
IEICE Transactions 94-C, No. 4, 401-410 (2011).
12
Encoder adaptable difference detection for low power video compression in surveillance system (English)
Sig. Proc.: Image Comm. 26, No. 3, 130-142 (2011).
13
Composite model-based DC dithering for suppressing contour artifacts in decompressed video (English)
IEEE Transactions on Image Processing 20, No. 8, 2110-2121 (2011).
14
Automatic spike detection based on real-time multi-channel template (English)
BMEI, 648-652 (2011).
15
Novel and efficient min cut based voltage assignment in gate level (English)
ISQED, 150-155 (2011).
16
Application-specific network-on-chip synthesis: cluster generation and network component insertion (English)
ISQED, 144-149 (2011).
17
Electromagnetic analysis enhancement with signal processing techniques (Poster) (English)
ACISP, 456-461 (2011).
18
A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering (English)
SiPS, 122-127 (2011).
19
A 98 gmacs/W 32-core vector processor in 65nm CMOS (English)
ISLPED, 373-378 (2011).
20
Result 1 to 20 of 290 total
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