Result 1 to 20 of 91 total
Composability and predictability for independent application development, verification, and execution. (English)
Hübner, Michael (ed.) et al., Multiprocessor system-on-chip. Hardware design and tool integration. New York, NY: Springer (ISBN 978-1-4419-6459-5/hbk; 978-1-4419-6460-1/ebook). 25-56 (2011).
1
A TDM slot allocation flow based on multipath routing in nocs (English)
Microprocessors and Microsystems - Embedded Hardware Design 35, No. 2, 130-138 (2011).
2
Design and implementation of an operating system for composable processor sharing (English)
Microprocessors and Microsystems - Embedded Hardware Design 35, No. 2, 246-260 (2011).
3
A quantitative evaluation of a network on chip design flow for multi-core consumer multimedia applications (English)
Design Autom. for Emb. Sys. 15, No. 2, 159-190 (2011).
4
Special issue on networks-on-chips: design flows and case studies (English)
Design Autom. for Emb. Sys. 15, No. 2, 87-88 (2011).
5
Interactive debug of socs with multiple clocks (English)
IEEE Design & Test of Computers 28, No. 3, 44-51 (2011).
6
Composability and predictability for independent application development, verification, and execution (English)
Multiprocessor System-on-Chip, 25-56 (2011).
7
Composable power management with energy and power budgets per application (English)
ICSAMOS, 396-403 (2011).
8
Time-predictable and composable architectures for dependable embedded systems (English)
EMSOFT, 351-352 (2011).
9
PUMA: placement unification with mapping and guaranteed throughput allocation on an FPGA using a hardwired noc (English)
DSD, 88-96 (2011).
10
Improved power modeling of DDR sdrams (English)
DSD, 99-108 (2011).
11
A non-intrusive online FPGA test scheme using a hardwired network on chip (English)
DSD, 351-359 (2011).
12
Power minimisation for real-time dataflow applications (English)
DSD, 117-124 (2011).
13
A unified execution model for data-driven applications on a composable mpsoc (English)
DSD, 818-822 (2011).
14
Composable local memory organisation for streaming applications on embedded mpsocs (English)
Conf. Computing Frontiers, 23 (2011).
15
Optimal scheduling of switched flexray networks (English)
DATE, 926-931 (2011).
16
Architectures and modeling of predictable memory controllers for improved system integration (English)
DATE, 851-856 (2011).
17
An FPGA bridge preserving traffic quality of service for on-chip network-based systems (English)
DATE, 425-430 (2011).
18
Memory controllers for high-performance and real-time mpsocs: requirements, architectures, and future trends (English)
CODES+ISSS, 3-12 (2011).
19
Bandwidth analysis of functional interconnects used as test access mechanism (English)
J. Electronic Testing 26, No. 4, 453-464 (2010).
20
Result 1 to 20 of 91 total
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