Result 1 to 20 of 20 total
A complete system-level behavioural model for IEEE 802.15.4 wireless sensor network simulations (English)
ISCAS, 3917-3920 (2010).
1
Systematic simulation-based predictive synthesis of integrated optical interconnect. (English)
IEEE Trans. VLSI Syst. 15, No. 8, 927-940 (2007).
2
Design of a novel CNTFET-based reconfigurable logic gate (English)
ISVLSI, 285-290 (2007).
3
Novel CNTFET-based reconfigurable logic gate design (English)
DAC, 276-277 (2007).
4
System level assessment of an optical noc in an mpsoc platform (English)
DATE, 1084-1089 (2007).
5
A family of ultra-fine grain CNTFET-based reconfigurable logic gates (English)
ReCoSoC, 177-185 (2007).
6
Heterogeneous modelling of an optical network-on-chip with systemc (English)
IEEE International Workshop on Rapid System Prototyping, 10-16 (2005).
7
VHDL \& VHDL-AMS modelling and simulation of a CMOS imager IP (English)
FDL, 179-183 (2005).
8
UML/XML based approach to hierarchical AMS synthesis (English)
FDL, 89-101 (2005).
9
io-port 71022036 O’connor, Ian;
Briere, Matthieu;
Drouard, Emmanuel;
Kazmierczak, Art;
Tissafi-Drissi, Faress;
Navarro, David;
Mieyeville, Fabien;
Dambre, Joni;
Stroobandt, Dirk;
Fedeli, Jean-Marc;
Lisik, Zbigniew;
Gaffiot, Frédéric
Towards reconfigurable optical networks on chip (English)
ReCoSoC, 121-128 (2005).
10
Simulation of electrical and optical interconnections for future VLSI ICs. (English)
Bubak, Marian (ed.) et al., Computational science ‒ ICCS 2004. 4th international conference, Kraków, Poland, June 6‒9, 2004. Proceedings, Part IV. Berlin: Springer (ISBN 3-540-22129-8/pbk). Lecture Notes in Computer Science 3039, 1037-1044 (2004).
11
Simulation of electrical and optical interconnections for future VLSI ics (English)
International Conference on Computational Science, 1037-1044 (2004).
12
RUNE: platform for automated design of integrated multi-domain systems. Application to high-speed CMOS photoreceiver front-ends (English)
DATE, 16-21 (2004).
13
Design and behavioral modeling tools for optical network-on-chip (English)
DATE, 738-739 (2004).
14
Optical versus electrical interconnections for clock distribution networks in new VLSI technologies (English)
PATMOS, 461-470 (2003).
15
Design methodologies for high-speed CMOS photoreceiver front-ends (English)
SBCCI, 323-328 (2003).
16
Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioural description language (English)
FDL, 151-163 (2003).
17
A VHDL-AMS library of hierarchical optoelectronic device models (English)
FDL, 7-19 (2003).
18
Design and optimization of optical links based on VHDL-AMS modeling (English)
BMAS, 62- (2000).
19
Automatic layout generation for CMOS analog transistors (English)
EURO-DAC, 54-58 (1994).
20
Result 1 to 20 of 20 total
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