Result 1 to 20 of 114 total
Dynamic last-level cache allocation to reduce area and power overhead in directory coherence protocols. (English)
Kaklamanis, Christos (ed.) et al., Euro-Par 2012 parallel processing. 18th international conference, Euro-Par 2012, Rhodes Island, Greece, August 27‒31, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-32819-0/pbk). Lecture Notes in Computer Science 7484, 206-218 (2012).
1
Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. (English)
Concurrency Comput. Pract. Exp. 23, No. 17, 2235-2248 (2011).
2
OBQA: smart and cost-efficient queue scheme for head-of-line blocking elimination in fat-trees. (English)
J. Parallel Distrib. Comput. 71, No. 11, 1460-1472 (2011).
3
Characterizing the impact of process variation on 45 nm NoC-based CMPs. (English)
J. Parallel Distrib. Comput. 71, No. 5, 651-663 (2011).
4
A communication-driven routing technique for application-specific NoCs. (English)
Int. J. Parallel Program. 39, No. 3, 357-374 (2011).
5
Cost-efficient on-chip routing implementations for CMP and mpsoc systems. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 4, 534-547 (2011).
6
A low-latency modular switch for CMP systems (English)
Microprocessors and Microsystems - Embedded Hardware Design 35, No. 8, 742-754 (2011).
7
Virtualizing network-on-chip resources in chip-multiprocessors (English)
Microprocessors and Microsystems - Embedded Hardware Design 35, No. 2, 230-245 (2011).
8
Fault-tolerant vertical link design for effective 3D stacking (English)
Computer Architecture Letters 10, No. 2, 41-44 (2011).
9
Spidergon stnoc design flow (English)
NOCS, 267-268 (2011).
10
Efficient routing implementation in complex systems-on-chip (English)
NOCS, 1-8 (2011).
11
Towards an efficient noc topology through multiple injection ports (English)
DSD, 165-172 (2011).
12
CASS introduction (English)
IPDPS Workshops, 716-717 (2011).
13
HPC-mesh: A homogeneous parallel concentrated mesh for fault-tolerance and energy savings (English)
ANCS, 69-80 (2011).
14
A distributed switch architecture for on-chip networks (English)
ICPP, 21-30 (2011).
15
PC-mesh: A dynamic parallel concentrated mesh (English)
ICPP, 642-651 (2011).
16
Combining congested-flow isolation and injection throttling in HPC interconnection networks (English)
ICPP, 662-672 (2011).
17
Noc reconfiguration for CMP virtualization (English)
NCA, 219-222 (2011).
18
High performance networks. (English)
D’Ambra, Pasqua (ed.) et al., Euro-Par 2010 ‒ parallel processing. 16th international Euro-Par conference, Ischia, Italy, August 31 ‒ September 3, 2010. Proceedings, Part II. Berlin: Springer (ISBN 978-3-642-15290-0/pbk). Lecture Notes in Computer Science 6272, 412 (2010).
19
Buffer management strategies to reduce hol blocking (English)
IEEE Trans. Parallel Distrib. Syst. 21, No. 6, 739-753 (2010).
20
Result 1 to 20 of 114 total
Start
Contact
Print
General Help
