Result 1 to 17 of 17 total
Blind cartography for side channel attacks: cross-correlation cartography. (English)
Int. J. Reconfig. Comput. 2012, Article ID 360242, 9 p. (2012).
1
First principal components analysis: a new side channel distinguisher. (English)
Rhee, Kyung-Hyune (ed.) et al., Information security and cryptology ‒ ICISC 2010. 13th international conference, Seoul, Korea, December 1‒3, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-24208-3/pbk). Lecture Notes in Computer Science 6829, 407-419 (2011).
2
Characterization of the electromagnetic side channel in frequency domain. (English)
Lai, Xuejia (ed.) et al., Information security and cryptology. 6th international conference, Inscrypt 2010, Shanghai, China, October 20‒24, 2010. Revised selected papers. Berlin: Springer (ISBN 978-3-642-21517-9/pbk). Lecture Notes in Computer Science 6584, 471-486 (2011).
3
Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques (English)
DATE, 1004-1009 (2011).
4
Exploiting dual-output programmable blocks to balance secure dual-rail logics. (English)
Int. J. Reconfig. Comput. 2010, Article ID 375245, 12 p. (2010).
5
Evaluation of power constant dual-rail logics countermeasures against DPA with design time security metrics (English)
IEEE Trans. Computers 59, No. 9, 1250-1263 (2010).
6
First principal components analysis: A new side channel distinguisher (English)
ICISC, 407-419 (2010).
7
Characterization of the electromagnetic side channel in frequency domain (English)
Inscrypt, 471-486 (2010).
8
Countering early evaluation: an approach towards robust dual-rail precharge logic (English)
WESS, 6 (2010).
9
Entropy-based power attack (English)
HOST, 1-6 (2010).
10
Cross-correlation cartography (English)
ReConFig, 268-273 (2010).
11
Evaluation of white-box and grey-box noekeon implementations in FPGA (English)
ReConFig, 310-315 (2010).
12
DPL on stratix II FPGA: what to expect? (English)
ReConFig, 243-248 (2009).
13
Combined SCA and DFA countermeasures integrable in a FPGA design flow (English)
ReConFig, 213-218 (2009).
14
An 8x8 run-time reconfigurable FPGA embedded in a soc (English)
DAC, 120-125 (2008).
15
Secured CAD back-end flow for power-analysis-resistant cryptoprocessors. (English)
IEEE Design and Test of Computers 24, No. 06, 546-555 (2007).
16
Secured CAD back-end flow for power-analysis-resistant cryptoprocessors (English)
IEEE Design & Test of Computers 24, No. 6, 546-555 (2007).
17
Result 1 to 17 of 17 total
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