Result 1 to 20 of 80 total
A design methodology for the automatic sizing of standard-cell libraries (English)
ACM Great Lakes Symposium on VLSI, 151-156 (2011).
1
A design methodology to implement memory accesses in high-level synthesis (English)
CODES+ISSS, 49-58 (2011).
2
Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 6, 911-924 (2010).
3
io-port 50152259 Bertels, Koen;
Sima, Vlad Mihai;
Yankova, Yana;
Kuzmanov, Georgi;
Luk, Wayne;
Coutinho, José Gabriel F.;
Ferrandi, Fabrizio;
Pilato, Christian;
Lattuada, Marco;
Sciuto, Donatella;
Michelotti, Andrea
Hartes: hardware-software codesign for heterogeneous multicore platforms (English)
IEEE Micro 30, No. 5, 88-97 (2010).
4
Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation (English)
GECCO, 1267-1274 (2010).
5
A fast heuristic for extending standard cell libraries with regular macro cells (English)
ISVLSI, 23-28 (2010).
6
Fine grain analysis of simulators accuracy for calibrating performance models (English)
International Symposium on Rapid System Prototyping, 1-7 (2010).
7
Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable mpsocs (English)
ASP-DAC, 799-804 (2010).
8
Combining target-independent analysis with dynamic profiling to build the performance model of a DSP (English)
CIT, 1895-1901 (2010).
9
A reconfigurable multiprocessor architecture for a reliable face recognition implementation (English)
DATE, 319-322 (2010).
10
Performance modeling of embedded applications with zero architectural knowledge (English)
CODES+ISSS, 277-286 (2010).
11
Hartes design flow for heterogeneous platforms (English)
ISQED, 330-338 (2009).
12
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems (English)
GECCO, 1435-1442 (2009).
13
Performance estimation for task graphs combining sequential path profiling and control dependence regions (English)
MEMOCODE, 131-140 (2009).
14
A multiprocessor self-reconfigurable JPEG2000 encoder (English)
IPDPS, 1-8 (2009).
15
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform (English)
ASP-DAC, 317-322 (2009).
16
HW/SW methodologies for synchronization in FPGA multiprocessors (English)
FPGA, 265-268 (2009).
17
Mapping pipelined applications onto heterogeneous embedded systems: a Bayesian optimization algorithm based approach (English)
CODES+ISSS, 443-452 (2009).
18
Improving evolutionary exploration to area-time optimization of FPGA designs (English)
Journal of Systems Architecture - Embedded Systems Design 54, No. 11, 1046-1057 (2008).
19
Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems (English)
ICSAMOS, 142-149 (2008).
20
Result 1 to 20 of 80 total
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