Result 1 to 20 of 30 total
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization. (English)
Ayala, José L. (ed.) et al., Integrated circuit and system design. Power and timing modeling, optimization, and simulation. 21st international workshop, PATMOS 2011, Madrid, Spain, September 26‒29, 2011. Proceedings. Berlin: Springer (ISBN 978-3-642-24153-6/pbk). Lecture Notes in Computer Science 6951, 204-213 (2011).
1
Parsimonious circuits for error-tolerant applications through probabilistic logic minimization (English)
PATMOS, 204-213 (2011).
2
Towards personalized medicine and monitoring for healthy living (English)
ISSCC, 516-517 (2011).
3
A circuit technology platform for medical data acquisition and communication: outline of a collaboration project within the swiss nano-tera.ch initiative (English)
DATE, 1472-1473 (2011).
4
Energy parsimonious circuit design through probabilistic pruning (English)
DATE, 764-769 (2011).
5
MEMS-based all-digital frequency synthesis for ultralow-power radio for WBAN and WSN applications (English)
ISCAS, 157-160 (2011).
6
A 5.4dBm 42mW 2.4GHz CMOS BAW-based quasi-direct conversion transmitter (English)
ISSCC, 498-499 (2010).
7
Detailed analysis of a phase ADC (English)
ISCAS, 4273-4276 (2010).
8
Analysis of ultralow-power asynchronous adcs (English)
ISCAS, 3593-3596 (2010).
9
A multiband concurrent sampling based RF front end for biotelemetry applications (English)
ISCAS, 2948-2951 (2010).
10
Realization of a low-voltage and low-power colpitts quadrature oscillator (English)
ISCAS (2006).
12
On an implementation of differential and quadrature colpitts injection-locked frequency dividers (English)
ISCAS (2006).
13
Energy-efficient broadcasting in all-wireless networks. (English)
Wirel. Netw. 11, No. 1-2, 177-188 (2005).
14
WiseNET: An Ultralow-Power Wireless Sensor Network Solution. (English)
Computer 37, No.08, 62-70 (2004).
15
A MOS transistor model for mixed analog-digital circuit design and simulation. (English)
Reis, Ricardo (ed.) et al., Design of system on a chip. Boston, MA: Kluwer Academic Publishers (ISBN 1-4020-7928-1/hbk). 49-95 (2004).
16
Wisenet: an ultralow-power wireless sensor network solution (English)
IEEE Computer 37, No. 8, 62-70 (2004).
17
A novel I/Q mismatch compensation scheme for a low-IF receiver front-end (English)
ISCAS (4), 453-456 (2004).
18
Digital receiver architectures for the IEEE 802.15.4 standard (English)
ISCAS (4), 345-348 (2004).
19
Wisemac, an ultra low power MAC protocol for the wisenet wireless sensor network (English)
SenSys, 302-303 (2003).
20
Result 1 to 20 of 30 total
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