Result 1 to 17 of 17 total
Asynchronous switching for low-power networks-on-chip (English)
Microelectronics Journal 42, No. 12, 1370-1379 (2011).
1
Modeling of RLC interconnect lines (English)
ISCAS, 3889-3892 (2010).
2
Power characteristics of networks on chip (English)
ISCAS, 3721-3724 (2010).
3
Asynchronous BFT for low power networks on chip (English)
ISCAS, 3240-3243 (2010).
4
High throughput architecture for high performance noc (English)
ISCAS, 2241-2244 (2009).
5
High throughput architecture for OCTAGON network on chip (English)
ICECS, 101-104 (2009).
6
Power efficient networks on chip (English)
ICECS, 105-108 (2009).
7
High throughput architecture for CLICHÉ network on chip (English)
SoCC, 155-158 (2009).
8
Optimum wire tapering for minimum power dissipation in RLC interconnects (English)
ISCAS (2006).
9
Exponentially tapered h-tree clock distribution networks. (English)
IEEE Trans. VLSI Syst. 13, No. 8, 971-975 (2005).
10
Shielding effect of on-chip interconnect inductance. (English)
IEEE Trans. VLSI Syst. 13, No. 3, 396-400 (2005).
11
Power characteristics of inductive interconnect. (English)
IEEE Trans. VLSI Syst. 12, No. 12, 1295-1306 (2004).
12
Exponentially tapered H-tree clock distribution networks (English)
ISCAS (2), 601-604 (2004).
13
1-V ADPCM processor for low-power wireless applications (English)
VLSI-SOC, 386-393 (2003).
14
Optimum wire sizing of RLC interconnect with repeaters (English)
ACM Great Lakes Symposium on VLSI, 27-32 (2003).
15
Shielding effect of on-chip interconnect inductance (English)
ACM Great Lakes Symposium on VLSI, 165-170 (2003).
16
Inductive interconnect width optimization for low power (English)
ISCAS (5), 273-276 (2003).
17
Result 1 to 17 of 17 total
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