Result 1 to 20 of 38 total
Value prediction and speculative execution on GPU. (English)
Int. J. Parallel Program. 39, No. 5, 533-552 (2011).
1
Rematerialization-based register allocation through reverse computing (English)
Conf. Computing Frontiers, 24 (2011).
2
Speculative execution on GPU: an exploratory study (English)
ICPP, 453-461 (2010).
3
A theoretical framework for value prediction in parallel systems (English)
ICPP, 11-20 (2010).
4
Spatial complexity of reversibly computable DAG (English)
CASES, 47-56 (2009).
5
The foundation of self-developing blob machines for spatial computing. (English)
Physica D 237, No. 9, 1282-1301 (2008).
6
Programming self developing blob machines for spatial computing (English)
Computing Media and Languages for Space-Oriented Computation (2007).
7
$N$-synchronous kahn networks: a relaxed model of synchrony for real-time systems (English)
POPL, 180-193 (2006).
8
Synchronization of periodic clocks (English)
EMSOFT, 339-342 (2005).
9
Early periodic register allocation on ILP processors. (English)
Parallel Process. Lett. 14, No. 2, 287-313 (2004).
10
Early control of register pressure for software pipelined loops. (English)
Hedin, Görel (ed.), Compiler construction. 12th international conference, CC 2003, held as part of the joint European conferences on theory and practice of software, ETAPS 2003, Warsaw, Poland, April 7-11, 2003. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2622, 17-32 (2003).
11
Early control of register pressure for software pipelined loops (English)
CC, 17-32 (2003).
12
Circular-arc graph coloring: On chords and circuits in the meeting graph. (English)
Eur. J. Oper. Res. 136, No.3, 483-500 (2002).
13
Topic 08+13. Instruction-level parallelism and computer architecture. (English)
Sakellariou, Rizos (ed.) et al., Euro-Par 2001 Parallel processing. 7th international Euro-Par conference, Manchester, GB, August 28-31, 2001. Proceedings. Berlin: Springer. Lect. Notes Comput. Sci. 2150, 385 (2001).
14
Topic 08+13: instruction-level parallelism and computer architecture (English)
Euro-Par, 385 (2001).
15
Handling global constraints in compiler strategy. (English)
Int. J. Parallel Program. 28, No. 4, 325-345 (2000).
16
Handling global constraints in compiler strategy. (English)
Int. J. Parallel Program. 28, No. 4, 325-345 (2000).
17
On a graph-theoretical model for cyclic register allocation. (English)
Discrete Appl. Math. 93, No.2-3, 191-203 (1999).
18
Result 1 to 20 of 38 total