Spur-free multirate all-digital PLL for mobile phones in 65 nm CMOS (English)
J. Solid-State Circuits 46, No. 12, 2904-2919 (2011).
1
Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences (English)
IEEE Trans. on Circuits and Systems 58-I, No. 9, 2051-2060 (2011).
2
Spur-free all-digital PLL in 65nm for mobile phones (English)
ISSCC, 52-54 (2011).
3
Spurious free time-to-digital conversion in an ADPLL using short dithering sequences (English)
CICC, 1-4 (2010).
4
A quad-band receiver for GSM/GPRS/EDGE in 90 nm digital CMOS (English)
ISCAS (2006).
5
Design trade-offs of a symmetric linearized CMOS LC VCO (English)
ISCAS (4), 397-400 (2002).
6
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