Result 1 to 20 of 24 total
Exploiting near symmetry in multilevel logic synthesis. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 17, No. 9, 772-781 (1998).
1
Generating minimal covers of symmetric functions. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 12, No. 5, 710-713 (1993).
2
Multilevel logic synthesis with extended arrays. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 11, No. 2, 142-157 (1992).
3
Three Decades of HDLs: Part I, CDL Through TI-HDL. (English)
IEEE Design and Test of Computers 09, No.02, 69-81 (1992).
4
Three decades of hdls: part I, CDL through TI-HDL (English)
IEEE Design & Test of Computers 9, No. 2, 69-81 (1992).
5
Multilevel logic synthesis of symmetric switching functions. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 10, No. 4, 436-446 (1991).
6
Local transformations via cube operations. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 6, No. 5, 892-902 (1987).
7
CONLAN report. (English)
Lecture Notes in Computer Science, 151. Berlin-Heidelberg New York - Tokyo: Springer-Verlag. XII, 174 p. DM 23.00; \$ 10.00 (1983).
8
CONLAN report (English)
Lecture Notes in Computer Science 151 (1983).
9
An overview of CONLAN: A formal construction method for hardware description language (English)
IFIP Congress, 199-204 (1980).
10
CONLAN: a formal construction method for hardware description languages: basic principles (English)
AFIPS National Computer Conference, 209-217 (1980).
11
CONLAN: a formal construction method for hardware description languages: language derivation (English)
AFIPS National Computer Conference, 219-227 (1980).
12
CONLAN: a formal construction method for hardware description languages: language application (English)
AFIPS National Computer Conference, 229-236 (1980).
13
Fast state minimization of incompletely specified sequential machines. (English)
IEEE Trans. Comput. 22, No. 02, 215-217 (1973).
14
Fast state minimization of incompletely specified sequential machines. (English)
IEEE Trans. Comput. 22, 215-217 (1973).
15
The avoidance and elimination of function hazards in asynchronous sequential circuits. (English)
IEEE Trans. Comput. 20, No. 02, 184-189 (1971).
16
Logic design of digital systems. (English)
The Allyn and Bacon Series in Electrical Engineering. Boston, Mass.: Allyn and Bacon, Inc. VIII, 800 p. \$ 16.95 (1971).
17
The avoidance and elimination of function hazards in asynchronous sequential circuits. (English)
IEEE Trans. Comput. 20, 184-189 (1971).
18
Translation of a DDL digital system specification to Boolean equations. (English)
IEEE Trans. Comput. 18, No. 04, 305-313 (1969).
19
Computer reduction of two-level, multiple-output switching circuits. (English)
IEEE Trans. Comput. 18, No. 01, 58-63 (1969).
20
Result 1 to 20 of 24 total
Start
Contact
Print
General Help
