Result 1 to 13 of 13 total
Weighted transition based reordering, columnwise bit filling, and difference vector: a power-aware test data compression method. (English)
VLSI Des. 2011, Article ID 756561, 8 p. (2011).
1
Suitability of various low-power testing techniques for IP core-based SoC: a survey. (English)
VLSI Des. 2011, Article ID 948926, 7 p. (2011).
2
Weighted transition based reordering, columnwise bit filling, and difference vector: A power-aware test data compression method (English)
VLSI Design 2011 (2011).
3
Suitability of various low-power testing techniques for IP core-based soc: A survey (English)
VLSI Design 2011 (2011).
4
A novel OTA and FVF based second generation current conveyor (English)
ICWET, 1044-1048 (2011).
5
Run-length-based test data compression techniques: how far from entropy and power bounds? A survey. (English)
VLSI Des. 2010, Article ID 670476, 9 p. (2010).
6
Run-length-based test data compression techniques: how far from entropy and power bounds? - A survey (English)
VLSI Design 2010 (2010).
7
Modified selective Huffman coding for optimization of test data compression, test application time and area overhead (English)
J. Electronic Testing 26, No. 6, 679-688 (2010).
8
Combining unspecified test data bit filling methods and run length based codes to estimate compression, power and area overhead (English)
ISVLSI, 448-449 (2010).
9
Low voltage, high folding rate folding amplifier (English)
ICWET, 899-902 (2010).
10
Hamming distance based reordering and columnwise bit stuffing with difference vector: A better scheme for test data compression with run length based codes (English)
VLSI Design, 33-38 (2010).
11
Low voltage, low power folding amplifier for folding \& interpolating ADC (English)
ARTCom, 178-182 (2009).
12
Survey of test data compression technique emphasizing code based schemes (English)
DSD, 617-620 (2009).
13
Result 1 to 13 of 13 total
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