Result 1 to 20 of 108 total
Handbook of signal processing systems. Foreword by S. Y. Kung. (English)
New York, NY: Springer (ISBN 978-1-4419-6344-4/hbk; 978-1-4419-6345-1/ebook). xxxviii, 1083~p. EUR~189.95/net; SFR~286.50; \sterling~166.50; \$~249.00 (2010).
1
Realizing FIFO communication when mapping Kahn process networks onto the cell. (English)
Bertels, Koen (ed.) et al., Embedded computer systems: Architectures, modeling, and simulation. 9th international workshop, SAMOS 2009, Samos, Greece, July 20‒23, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-03137-3/pbk). Lecture Notes in Computer Science 5657, 308-317 (2009).
2
Introduction to mastering cell BE and GPU execution platforms. (English)
Bertels, Koen (ed.) et al., Embedded computer systems: Architectures, modeling, and simulation. 9th international workshop, SAMOS 2009, Samos, Greece, July 20‒23, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-03137-3/pbk). Lecture Notes in Computer Science 5657, 275-276 (2009).
3
Realizing FIFO communication when mapping kahn process networks onto the cell (English)
SAMOS, 308-317 (2009).
4
Introduction to mastering cell BE and GPU execution platforms (English)
SAMOS, 275-276 (2009).
5
Automated integration of dedicated hardwired IP cores in heterogeneous mpsocs designed with ESPAM. (English)
EURASIP J. Embed. Syst. 2008, Article ID 726096, 15 p. (2008).
6
Deriving efficient control in process networks with compaan/Laura. (English)
Int. J. Embed. Syst. 3, No. 3, 170-180 (2008).
7
Systematic and automated multiprocessor system design, programming, and implementation. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27, No. 3, 542-555 (2008).
8
Tool integration and interoperability challenges of a system-level design flow: A case study. (English)
Bereković, Mladen (ed.) et al., Embedded computer systems: Architectures, modeling, and simulation. 8th international workshop, SAMOS 2008, Samos, Greece, July 21‒24, 2008. Proceedings. Berlin: Springer (ISBN 978-3-540-70549-9/pbk). Lecture Notes in Computer Science 5114, 167-176 (2008).
9
Automated integration of dedicated hardwired IP cores in heterogeneous mpsocs designed with ESPAM (English)
EURASIP J. Emb. Sys. 2008 (2008).
10
Tool integration and interoperability challenges of a system-level design flow: A case study (English)
SAMOS, 167-176 (2008).
11
Hierarchical run time deadlock detection in process networks (English)
SiPS, 239-244 (2008).
12
Daedalus: toward composable multimedia MP-soc design (English)
DAC, 574-579 (2008).
13
Classifying interprocess communication in process network representation of nested-loop programs. (English)
ACM Trans Embed. Comput. Syst. 6, No. 2 (2007).
14
Transforming signal processing applications into parallel implementations (English)
EURASIP J. Adv. Sig. Proc. 2007 (2007).
15
Parameterized looped schedules for compact representation of execution sequences in DSP hardware and software implementation (English)
IEEE Transactions on Signal Processing 55, No. 6-2, 3126-3138 (2007).
16
Efficient external memory interface for multi-processor platforms realized on FPGA chips (English)
FPL, 580-584 (2007).
17
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-socs (English)
CODES+ISSS, 9-14 (2007).
18
FPGA implementation of a prototype hierarchical control network for large-scale signal processing applications. (English)
Nagel, Wolfgang E. (ed.) et al., Euro-Par 2006 parallel processing. 12th international Euro-Par conference, Dresden, Germany, August 28‒September 1, 2006. Proceedings. Berlin: Springer (ISBN 978-3-540-37783-2/pbk). Lecture Notes in Computer Science 4128, 1192-1203 (2006).
19
Requirements for interfacing iP-components in re-configurable platforms. (English)
J. VLSI Signal Process. 43, No. 2-3, 173-184 (2006).
20
Result 1 to 20 of 108 total
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