High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis. (English)
Int. J. Reconfig. Comput. 2011, Article ID 406857, 17 p. (2011).
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TRETS 3, No. 1 (2010).
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High-level synthesis techniques for in-circuit assertion-based verification (English)
IPDPS Workshops, 1-8 (2010).
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FCCM, 23-30 (2008).
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ESA, 169-175 (2006).
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