Result 1 to 17 of 17 total
Exploring the effects of on-chip thermal variation on high-performance multicore architectures. (English)
ACM Trans. Archit. Code Optim. 8, No. 1, 2 (2011).
1
io-port 70203478 Jiménez, Victor;
Cazorla, Francisco J.;
Gioiosa, Roberto;
Valero, Mateo;
Boneti, Carlos;
Kursun, Eren;
Cher, Chen-Yong;
Isci, Canturk;
Buyuktosunoglu, Alper;
Bose, Pradip
Power and thermal characterization of POWER6 system (English)
PACT, 7-18 (2010).
2
Trends and techniques for energy efficient architectures (English)
VLSI-SoC, 276-279 (2010).
3
io-port 70219341 Bose, Pradip;
Buyuktosunoglu, Alper;
Cher, Chen-Yong;
Darringer, John A.;
Gupta, Meeta Sharma;
Hamann, Hendrik F.;
Jacobson, Hans M.;
Kudva, Prabhakar;
Kursun, Eren;
Madan, Niti;
Nair, Indira;
Rivers, Jude A.;
Shin, Jeonghee;
Weger, Alan J.;
Zyuban, Victor V.
Power-efficient, reliable microprocessor architectures: modeling and design methods (English)
ACM Great Lakes Symposium on VLSI, 299-304 (2010).
4
io-port 70451894 Johnson, Charles L.;
Allen, David H.;
Brown, Jeffrey D.;
Vanderwiel, Steve;
Hoover, Russ;
Achilles, Heather D.;
Cher, Chen-Yong;
May, George A.;
Franke, Hubertus;
Xenedis, Jimi;
Basso, Claude
A wire-speed $power^{TM}$ processor: 2.3GHz 45nm SOI with 16 cores and 64 threads (English)
ISSCC, 104-105 (2010).
5
Performance and power evaluation of an in-line accelerator (English)
Conf. Computing Frontiers, 81-82 (2010).
6
Temperature variation characterization and thermal management of multicore architectures (English)
IEEE Micro 29, No. 1, 116-126 (2009).
7
Software-controlled priority characterization of POWER5 processor (English)
ISCA, 415-426 (2008).
8
Cell GC: using the cell synergistic processor as a garbage collection coprocessor (English)
VEE, 141-150 (2008).
9
Variation-aware thermal characterization and management of multi-core architectures (English)
ICCD, 280-285 (2008).
10
Thermal-aware task scheduling at the system software level (English)
ISLPED, 213-218 (2007).
11
Do trace cache, value prediction and prefetching improve SMT throughput? (English)
ARCS, 232-251 (2006).
12
An analysis of efficient multi-core global power management policies: maximizing performance for a given power budget (English)
MICRO, 347-358 (2006).
13
Combined circuit and architectural level variable supply-voltage scaling for low power. (English)
IEEE Trans. VLSI Syst. 13, No. 5, 564-576 (2005).
14
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign (English)
ASPLOS, 199-210 (2004).
15
VSV: L2-miss-driven variable supply-voltage scaling for low power (English)
MICRO, 19-28 (2003).
16
Skipper: a microarchitecture for exploiting control-flow independence (English)
MICRO, 4-15 (2001).
17
Result 1 to 17 of 17 total
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