Result 1 to 20 of 66 total
Dynamic cache partitioning based on the MLP of cache misses. (English)
Stenström, Per (ed.), Transactions on High-Performance Embedded Architectures and Compilers III. Berlin: Springer (ISBN 978-3-642-19447-4/pbk). Lecture Notes in Computer Science 6590. Journal Subline, 3-23 (2011).
1
Dynamic cache partitioning based on the MLP of cache misses (English)
T. HiPEAC 3, 3-23 (2011).
2
Energy-aware accounting and billing in large-scale computing facilities (English)
IEEE Micro 31, No. 3, 60-71 (2011).
3
A quantitative analysis of OS noise (English)
IPDPS, 852-863 (2011).
4
Hybrid high-performance low-power and ultra-low energy reliable caches (English)
Conf. Computing Frontiers, 12 (2011).
5
A software-pipelined approach to multicore execution of timing predictable multi-threaded hard real-time tasks (English)
ISORC, 233-240 (2011).
6
Towards improved survivability in safety-critical systems (English)
IOLTS, 240-245 (2011).
7
RVC-based time-predictable faulty caches for safety-critical systems (English)
IOLTS, 25-30 (2011).
8
IA^3: an interference aware allocation algorithm for multicore hard real-time systems (English)
IEEE Real-Time and Embedded Technology and Applications Symposium, 280-290 (2011).
9
RVC: a mechanism for time-analyzable real-time processors with faulty caches (English)
HiPEAC, 97-106 (2011).
10
io-port 50151685 Ungerer, Theo;
Cazorla, Francisco J.;
Sainrat, Pascal;
Bernat, Guillem;
Petrov, Zlatko;
Rochange, Christine;
Quiñones, Eduardo;
Gerdes, Mike;
Paolieri, Marco;
Wolf, Julian;
Cassé, Hugues;
Uhrig, Sascha;
Guliashvili, Irakli;
Houston, Michael;
Kluge, Florian;
Metzlaff, Stefan;
Mische, Jörg
Merasa: multicore execution of hard real-time applications supporting analyzability (English)
IEEE Micro 30, No. 5, 66-75 (2010).
11
On the problem of evaluating the performance of multiprogrammed workloads (English)
IEEE Trans. Computers 59, No. 12, 1722-1728 (2010).
12
io-port 70203478 Jiménez, Victor;
Cazorla, Francisco J.;
Gioiosa, Roberto;
Valero, Mateo;
Boneti, Carlos;
Kursun, Eren;
Cher, Chen-Yong;
Isci, Canturk;
Buyuktosunoglu, Alper;
Bose, Pradip
Power and thermal characterization of POWER6 system (English)
PACT, 7-18 (2010).
13
Trends and techniques for energy efficient architectures (English)
VLSI-SoC, 276-279 (2010).
14
Adapting cache partitioning algorithms to pseudo-LRU replacement policies (English)
IPDPS, 1-12 (2010).
15
Load balancing using dynamic cache allocation (English)
Conf. Computing Frontiers, 153-164 (2010).
16
Thread to strand binding of parallel network applications in massive multi-threaded systems (English)
PPOPP, 191-202 (2010).
17
Flexdcp: a QoS framework for CMP architectures. (English)
Oper. Syst. Rev. 43, No. 2, 86-96 (2009).
18
CPU accounting in CMP processors (English)
Computer Architecture Letters 8, No. 1, 17-20 (2009).
19
An analyzable memory controller for hard real-time cmps (English)
Embedded Systems Letters 1, No. 4, 86-90 (2009).
20
Result 1 to 20 of 66 total
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