Result 1 to 20 of 82 total
Time-division-multiplexed arbitration in silicon nanophotonic networks-on-chip for high-performance chip multiprocessors. (English)
J. Parallel Distrib. Comput. 71, No. 5, 641-650 (2011).
1
Guest editorial: Special section on the ACM/IEEE symposium on networks-on-chip 2010. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 4, 492-493 (2011).
2
An integrated four-phase buck converter delivering $1A/mm^{2}$ with 700ps controller delay and network-on-chip load in 45-nm SOI (English)
CICC, 1-4 (2011).
3
Supervised design space exploration by compositional approximation of Pareto sets (English)
DAC, 399-404 (2011).
4
io-port 70424341 Stanje, Gerald;
Miller, Paul;
Zhu, Jianxun;
Smith, Alexander;
Winn, Olivia;
Margolies, Robert;
Gorlatova, Maria;
Sarik, John;
Szczodrak, Marcin;
Vigraham, Baradwaj;
Carloni, Luca P.;
Kinget, Peter R.;
Kymissis, Ioannis;
Zussman, Gil
Organic solar cell-equipped energy harvesting active networked tag (EnHANT) prototypes (English)
SenSys, 385-386 (2011).
5
A complete framework for programming event-driven, self-reconfigurable low power wireless networks (English)
SenSys, 415-416 (2011).
6
VANDAL: A tool for the design specification of nanophotonic networks (English)
DATE, 782-787 (2011).
8
Embedded processor virtualization for broadband grid computing (English)
GRID, 145-156 (2011).
9
A dynamic and distributed TDM slot-scheduling protocol for QoS-oriented networks-on-chip (English)
ICCD, 31-38 (2011).
10
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 6, 869-882 (2010).
11
Accurate predictive interconnect modeling for system-level design. (English)
IEEE Trans. VLSI Syst. 18, No. 4, 679-684 (2010).
12
Circuit-switched memory access in photonic interconnection networks for high-performance embedded computing (English)
SC, 1-12 (2010).
13
Message from the chairs (English)
MEMOCODE, 1-3 (2010).
14
Virtual channels vs. Multiple physical networks: a comparative analysis (English)
DAC, 162-165 (2010).
15
A heterogeneous parallel system running open mpi on a broadband network of embedded set-top devices (English)
Conf. Computing Frontiers, 187-196 (2010).
16
Exploiting local logic structures to optimize multi-core soc floorplanning (English)
DATE, 1291-1296 (2010).
17
Phoenixsim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks (English)
DATE, 691-696 (2010).
18
Recursion-driven parallel code generation for multi-core platforms (English)
DATE, 190-195 (2010).
19
Proceedings of the 10th international conference on embedded software, EMSOFT 2010, scottsdale, arizona, USA, October 24-29, 2010 (English)
EMSOFT (2010).
20
Result 1 to 20 of 82 total
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