Result 1 to 20 of 24 total
io-port 05914017 Grasset, Arnaud;
Millet, Philippe;
Bonnot, Philippe;
Yehia, Sami;
Putzke-Roeming, Wolfram;
Campi, Fabio;
Rosti, Alberto;
Huebner, Michael;
Voros, Nikolaus S.;
Rossi, Davide;
Sahlbach, Henning;
Ernst, Rolf
The MORPHEUS heterogeneous dynamically reconfigurable platform. (English)
Int. J. Parallel Program. 39, No. 3, 328-356 (2011).
1
Improving electro-magnetic interference of embedded systems through jittered-delay desynchronization. (English)
J. Low Power Electron. 6, No. 4, 607-615 (2010).
2
Signal and power integrity for socs (English)
ISSCC, 520 (2010).
3
A heterogeneous digital signal processor implementation for dynamically reconfigurable computing (English)
CICC, 641-644 (2009).
4
Design space exploration of an open-source, IP-reusable, scalable floating-point engine for embedded applications (English)
Journal of Systems Architecture - Embedded Systems Design 54, No. 12, 1143-1154 (2008).
5
io-port 50354401 Kühnle, Matthias;
Hübner, Michael;
Becker, Jürgen;
Deledda, Antonio;
Mucci, Claudio;
Ries, Florian;
Coppola, Marcello;
Pieralisi, Lorenzo;
Locatelli, Riccardo;
Maruccia, Giuseppe;
Demarco, Tommaso;
Campi, Fabio
An interconnect strategy for a heterogeneous, reconfigurable soc (English)
IEEE Design & Test of Computers 25, No. 5, 442-451 (2008).
6
Reconfigurable hardware: the holy grail of matching performance with programming productivity (English)
FPL, 409-414 (2008).
7
Sustainable (re-) configurable solutions for the high volume soc market (English)
IPDPS, 1-8 (2008).
8
io-port 70688379 Mucci, Claudio;
Vanzolini, Luca;
Mirimin, Ilario;
Gazzola, Daniele;
Deledda, Antonio;
Goller, Sebastian;
Knäblein, Joachim;
Schneider, Axel;
Ciccarelli, Luca;
Campi, Fabio
Implementation of parallel LFSR-based applications on an adaptive DSP featuring a pipelined configurable gate array (English)
DATE, 1444-1449 (2008).
9
io-port 70690333 Deledda, Antonio;
Mucci, Claudio;
Vitkovski, Arseni;
Bonnot, Philippe;
Grasset, Arnaud;
Millet, Philippe;
Kühnle, Matthias;
Ries, Florian;
Hübner, Michael;
Becker, Jürgen;
Coppola, Massimo;
Pieralisi, Lorenzo;
Locatelli, Riccardo;
Maruccia, Giuseppe;
Campi, Fabio;
Demarco, Tommaso
Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor (English)
DATE, 1352-1357 (2008).
10
Interactive presentation: implementation of AES/rijndael on a dynamically reconfigurable architecture (English)
DATE, 355-360 (2007).
11
A dynamically adaptive DSP for heterogeneous reconfigurable platforms (English)
DATE, 9-14 (2007).
12
A stream register file unit for reconfigurable processors (English)
ISCAS (2006).
13
A case-study on multimedia applications for the xirisc reconfigurable processor (English)
ISCAS (2006).
14
A low-power system-on-chip for the documentation of road accidents. (English)
IEEE Trans. Circuits Syst. Video Technol. 15, No. 11, 1493-1501 (2005).
15
A cycle-accurate ISS for a dynamically reconfigurable processor architecture (English)
IPDPS (2005).
16
Compact buffered routing architecture (English)
FPL, 179-188 (2004).
17
A dataflow control unit for C-to-configurable pipelines compilation flow (English)
FCCM, 332-333 (2004).
18
Routing architecture for multi-context fpgas (English)
FPGA, 246 (2004).
19
Decoder-based multi-context interconnect architecture (English)
ISVLSI, 231-233 (2003).
20
Result 1 to 20 of 24 total
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