New redundant logic design concept for high noise and low voltage scenarios (English)
Microelectronics Journal 42, No. 12, 1359-1369 (2011).
1
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations (English)
ISCAS, 2585-2588 (2011).
2
A new probabilistic design methodology of nanoscale digital circuits (English)
CONIELECOMP, 190-193 (2011).
3
A new compensation mechanism for environmental parameter fluctuations in CMOS digital ics (English)
Microelectronics Journal 40, No. 6, 952-957 (2009).
4
High level spectral-based analysis of power consumption in dsps systems (English)
ISCAS (2006).
5
Selective clock-gating for low-power synchronous counters. (English)
J. Low Power Electron. 1, No. 3, 217-225 (2005).
6
Discriminant grammars and generalized linear discriminant functions. (Spanish)
Qüestiió 13, No. 1-3, 31-46 (1989).
7
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