Result 1 to 20 of 56 total
A first step towards automatic application of power analysis countermeasures (English)
DAC, 230-235 (2011).
1
Graph-coloring and treescan register allocation using repairing (English)
CASES, 45-54 (2011).
2
Reducing the pressure on routing resources of fpgas with generic logic chains (English)
FPGA, 237-246 (2011).
3
An optimal linear-time algorithm for interprocedural register allocation in high level synthesis using SSA form. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 7, 1096-1109 (2010).
4
Fast, nearly optimal ISE identification with I/O serialization through maximal clique enumeration. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 3, 341-354 (2010).
5
Improving FPGA performance for carry-save arithmetic. (English)
IEEE Trans. VLSI Syst. 18, No. 4, 578-590 (2010).
6
Virtual ways: Efficient coherence for architecturally visible storage in automatic instruction set extensions. (English)
Patt, Yale N. (ed.) et al., High performance embedded architectures and compilers. 5th international conference, HiPEAC 2010, Pisa, Italy, January 25‒27, 2010. Proceedings. Berlin: Springer (ISBN 978-3-642-11514-1/pbk). Lecture Notes in Computer Science 5952, 126-140 (2010).
7
Synthesis of floating-point addition clusters on fpgas using carry-save arithmetic (English)
FPL, 19-24 (2010).
8
A high-level synthesis flow for custom instruction set extensions for application-specific processors (English)
ASP-DAC, 707-712 (2010).
9
Virtual ways: efficient coherence for architecturally visible storage in automatic instruction set extensions (English)
HiPEAC, 126-140 (2010).
10
Optimistic chordal coloring: a coalescing heuristic for SSA form programs. (English)
Des. Autom. Embed. Syst. 13, No. 1-2, 115-137 (2009).
11
An approximation algorithm for scheduling on heterogeneous reconfigurable resources. (English)
ACM Trans Embed. Comput. Syst. 9, No. 1 (2009).
12
A design flow and evaluation framework for DPA-resistant instruction set extensions. (English)
Clavier, Christophe (ed.) et al., Cryptographic hardware and embedded systems ‒ CHES 2009. 11th international workshop Lausanne, Switzerland, September 6‒9, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-04137-2/pbk). Lecture Notes in Computer Science 5747, 205-219 (2009).
13
MPSoC design using application-specific architecturally visible communication. (English)
Seznec, André (ed.) et al., High performance embedded architectures and compilers. Fourth international conference, HiPEAC 2009, Paphos, Cyprus, January 25‒28, 2009. Proceedings. Berlin: Springer (ISBN 978-3-540-92989-5/pbk). Lecture Notes in Computer Science 5409, 183-197 (2009).
14
Optimistic chordal coloring: a coalescing heuristic for SSA form programs (English)
Design Autom. for Emb. Sys. 13, No. 1-2, 115-137 (2009).
15
io-port 50328547 Cevrero, Alessandro;
Athanasopoulos, Panagiotis;
Parandeh-Afshar, Hadi;
Verma, Ajay K.;
Niaki, Seyed Hosein Attarzadeh;
Nicopoulos, Chrysostomos;
Gürkaynak, Frank K.;
Brisk, Philip;
Leblebici, Yusuf;
Ienne, Paolo
Field programmable compressor trees: acceleration of multi-input addition on fpgas (English)
TRETS 2, No. 2 (2009).
16
An FPGA logic cell and carry chain configurable as a 6: 2 or 7: 2 compressor (English)
TRETS 2, No. 3 (2009).
17
Using 3D integration technology to realize multi-context fpgas (English)
FPL, 507-510 (2009).
18
Exploiting fast carry-chains of fpgas for designing compressor trees (English)
FPL, 242-249 (2009).
19
Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applications (English)
SiPS, 115-120 (2009).
20
Result 1 to 20 of 56 total
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