Result 1 to 20 of 261 total
Fast statistical static timing analysis using smart Monte Carlo techniques. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 6, 852-865 (2011).
1
A robust edge encoding technique for energy-efficient multi-cycle interconnect. (English)
IEEE Trans. VLSI Syst. 19, No. 2, 264-273 (2011).
2
Dynamic NBTI management using a 45 nm multi-degradation sensor (English)
IEEE Trans. on Circuits and Systems 58-I, No. 9, 2026-2037 (2011).
3
A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers (English)
ISQED, 87-90 (2011).
4
Energy-optimized high performance FFT processor (English)
ICASSP, 1701-1704 (2011).
5
Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T srams (English)
ISLPED, 145-150 (2011).
6
Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design (English)
DAC, 990-995 (2011).
7
io-port 70451999 Chen, Gregory K.;
Ghaed, Hassan;
Haque, Razi-Ul;
Wieckowski, Michael;
Kim, Yejoong;
Kim, Gyouho;
Fick, David;
Kim, Daeyeon;
Seok, Mingoo;
Wise, Kensall;
Blaauw, David;
Sylvester, Dennis
A cubic-millimeter energy-autonomous wireless intraocular pressure monitor (English)
ISSCC, 310-312 (2011).
8
A 660pW multi-stage temperature-compensated timer for ultra-low-power wireless sensor node synchronization (English)
ISSCC, 46-48 (2011).
9
A 0.27V 30MHz 17.7nJ/transform 1024-pt complex FFT core with super-pipelining (English)
ISSCC, 342-344 (2011).
10
Low power interconnects for SIMD computers (English)
DATE, 600-605 (2011).
11
A confidence-driven model for error-resilient computing (English)
DATE, 1608-1613 (2011).
12
A dense 45nm half-differential SRAM with lower minimum operating voltage (English)
ISCAS, 57-60 (2011).
13
A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme (English)
ISCAS, 69-72 (2011).
14
Mechanical stress aware optimization for leakage power reduction. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 5, 722-736 (2010).
15
Yield-driven near-threshold SRAM design. (English)
IEEE Trans. VLSI Syst. 18, No. 11, 1590-1598 (2010).
16
Victim alignment in crosstalk-aware timing analysis. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 2, 261-274 (2010).
17
Clock network design for ultra-low power applications (English)
ISLPED, 271-276 (2010).
18
Dynamic NBTI management using a 45nm multi-degradation sensor (English)
CICC, 1-4 (2010).
19
Analyzing the impact of double patterning lithography on SRAM variability in 45nm CMOS (English)
CICC, 1-4 (2010).
20
Result 1 to 20 of 261 total
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