Result 1 to 20 of 25 total
Radiale: A framework for designing and assessing link quality estimators in wireless sensor networks. (English)
Ad Hoc Netw. 9, No. 7, 1165-1185 (2011).
1
An efficient gate library for ambipolar CNTFET logic. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 30, No. 2, 242-255 (2011).
2
Regular nanofabrics in emerging technologies - design and fabrication methods for nanoscale digital circuits (English)
Lecture Notes in Electrical Engineering 82, 1-188 (2011).
3
Can we go towards true 3-D architectures? (English)
DAC, 282-283 (2011).
4
Evaluation of a crossbar multiplexer in a lithography-based nanowire technology (English)
ISCAS, 2930-2933 (2011).
5
F-LQE: A fuzzy link quality estimator for wireless sensor networks. (English)
Silva, Jorge Sá (ed.) et al., Wireless sensor networks. 7th European conference, EWSN 2010, Coimbra, Portugal, February 17‒19, 2010. Proceedings. Berlin: Springer (ISBN 978-3-642-11916-3/pbk). Lecture Notes in Computer Science 5970, 240-255 (2010).
6
Phase-change-memory-based storage elements for configurable logic (English)
FPT, 17-20 (2010).
7
Power consumption of logic circuits in ambipolar carbon nanotube technology (English)
DATE, 303-306 (2010).
8
Memristive devices fabricated with silicon nanowire Schottky barrier transistors (English)
ISCAS, 9-12 (2010).
9
Characterization of memristive poly-si nanowires via empirical physical modelling (English)
ISCAS, 1675-1678 (2010).
10
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors (English)
ISCAS, 1715-1718 (2010).
11
F-LQE: A fuzzy link quality estimator for wireless sensor networks (English)
EWSN, 240-255 (2010).
12
A testbed for the evaluation of link quality estimators in wireless sensor networks (English)
AICCSA, 1-8 (2010).
13
Synthesis of regular computational fabrics with ambipolar CNTFET technology (English)
ICECS, 70-73 (2010).
14
Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics (English)
ICECS, 66-69 (2010).
15
Emerging memory technologies for reconfigurable routing in FPGA architecture (English)
ICECS, 62-65 (2010).
16
Decoding nanowire arrays fabricated with the multi-spacer patterning technique (English)
DAC, 77-82 (2009).
17
A comparative simulation study of link quality estimators in wireless sensor networks (English)
MASCOTS, 1-10 (2009).
18
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique (English)
CASES, 11-16 (2009).
19
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories (English)
ASP-DAC, 835-840 (2009).
20
Result 1 to 20 of 25 total
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