io-port.net

io-port 50182879 Baldwin, Brian; Byrne, Andrew; Lu, Liang; Hamilton, Mark; Hanley, Neil; O’neill, Máire; Marnane, William P.

A hardware wrapper for the SHA-3 hash algorithms (English)

IACR Cryptology ePrint Archive 2010, 124 (2010).

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io-port 70068569 Baldwin, Brian; Byrne, Andrew; Lu, Liang; Hamilton, Mark; Hanley, Neil; O’neill, Máire; Marnane, William P.

FPGA implementations of the round two SHA-3 candidates (English)

FPL, 400-407 (2010).

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io-port 05529622 Baldwin, Brian; Moloney, Richard; Byrne, Andrew; McGuire, Gary; Marnane, William P.

A hardware analysis of twisted Edwards curves for an elliptic curve cryptosystem. (English)

Becker, Jürgen (ed.) et al., Reconfigurable computing: Architectures, tools and applications. 5th international workshop, ARC 2009, Karlsruhe, Germany, March 16‒18, 2009. Proceedings. Berlin: Springer (ISBN 978-3-642-00640-1/pbk). Lecture Notes in Computer Science 5453, 355-361 (2009).

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io-port 50181941 Baldwin, Brian; Marnane, William P.

An FPGA technologies area examination of the SHA-3 hash candidate implementations (English)

IACR Cryptology ePrint Archive 2009, 603 (2009).

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io-port 50182305 Baldwin, Brian; Byrne, Andrew; Hamilton, Mark; Hanley, Neil; Mcevoy, Robert P.; Pan, Weibo; Marnane, William P.

FPGA implementations of SHA-3 candidates: cubehash, grøstl, Lane, shabal and spectral hash (English)

IACR Cryptology ePrint Archive 2009, 342 (2009).

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io-port 50183093 Baldwin, Brian; Moloney, Richard; Byrne, Andrew; Mcguire, Gary; Marnane, William P.

A hardware analysis of twisted edwards curves for an elliptic curve cryptosystem (English)

IACR Cryptology ePrint Archive 2009, 1 (2009).

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io-port 50183337 Bailey, Daniel V.; Baldwin, Brian; Batina, Lejla; Bernstein, Daniel J.; Birkner, Peter; Bos, Joppe W.; Van Damme, Gauthier; De Meulenaer, Giacomo; Fan, Junfeng; Güneysu, Tim; Gürkaynak, Frank K.; Kleinjung, Thorsten; Lange, Tanja; Mentens, Nele; Paar, Christof; Regazzoni, Francesco; Schwabe, Peter; Uhsadel, Leif

The certicom challenges ECC2-X (English)

IACR Cryptology ePrint Archive 2009, 466 (2009).

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io-port 70197861 Baldwin, Brian; Byrne, Andrew; Hamilton, Mark; Hanley, Neil; Mcevoy, Robert P.; Pan, Weibo; Marnane, William P.

FPGA implementations of SHA-3 candidates: cubehash, grostl, Lane, shabal and spectral hash (English)

DSD, 783-790 (2009).

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io-port 70762982 Baldwin, Brian; Moloney, Richard; Byrne, Andrew; Mcguire, Gary; Marnane, William P.

A hardware analysis of twisted edwards curves for an elliptic curve cryptosystem (English)

ARC, 355-361 (2009).

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io-port 70796620 Baldwin, Brian; Marnane, William P.; Granger, Robert

Reconfigurable hardware implementation of arithmetic modulo minimal redundancy cyclotomic primes for ECC (English)

ReConFig, 255-260 (2009).

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io-port 70130379 Baldwin, Breck; Carpenter, Bob; Ross, Aaron

Alias-i threat trackers (English)

HLT-NAACL (2003).

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io-port 70193033 Bagga, Amit; Baldwin, Breck

Entity-based cross-document coreferencing using the vector space model (English)

COLING-ACL, 79-85 (1998).

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io-port 70446081 Baldwin, Bernard; Geiger, Davi; Hummel, Robert A.

Resolution-appropriate shape representation (English)

ICCV, 460-468 (1998).

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io-port 70013408 Baldwin, Breck; Doran, Christine; Reynar, Jeffrey C.; Niv, Michael; Srinivas, Bangalore

EAGLE: an extensible architecture for general linguistic engineering (English)

ANLP, 23- (1997).

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io-port 70876836 Baldwin, Breck; Doran, Christine; Reynar, Jeffrey C.; Niv, Michael; Srinivas, Bangalore; Wasson, Mark

EAGLE: an extensible architecture for general linguistic engineering (English)

RIAO, 271-284 (1997).

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io-port 70139348 Baldwin, Breck; Collins, Mike; Eisner, Jason; Ratnaparkhi, Adwait; Rosenzweig, Joseph; Sarkar, Anoop

University of pennsylvania: description of the university of pennsylvania system used for MUC-6 (English)

MUC, 177-191 (1995).

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io-port 70190523 Webber, Bonnie L.; Baldwin, Breck

Accommodating context change (English)

ACL, 96-103 (1992).

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