Result 1 to 20 of 41 total
Adaptive inter-layer message routing in 3D networks-on-chip (English)
Microprocessors and Microsystems - Embedded Hardware Design 35, No. 7, 613-631 (2011).
1
Bottom-up digital system-level reliability modeling (English)
CICC, 1-4 (2011).
2
I-BIRAS: interconnect built-in self-repair and adaptive serialization in 3D integrated systems (English)
European Test Symposium, 208 (2011).
3
Efficient fault detection architecture design of latch-based low power DSP/MCU processor (English)
European Test Symposium, 93-98 (2011).
4
Memory BIST with address programmability (English)
IOLTS, 79-85 (2011).
5
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks (English)
European Test Symposium, 258 (2010).
6
Error resilience of intra-die and inter-die communication with 3D spidergon stnoc (English)
DATE, 275-278 (2010).
7
RILM: reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip (English)
IOLTS, 121-126 (2010).
8
Interconnect built-in self-repair and adaptive-serialization (I-BIRAS) for 3D integrated systems (English)
IOLTS, 218 (2010).
9
Configurable serial fault-tolerant link for communication in 3D integrated systems (English)
IOLTS, 115-120 (2010).
10
An effective approach to detect logic soft errors in digital circuits based on GRAAL (English)
ISQED, 236-240 (2009).
11
HOT TOPIC - concurrent soc development and end-to-end planning (English)
DATE, 430 (2009).
12
Coordinated versus uncoordinated checkpoint recovery for network-on-chip based systems (English)
DELTA, 32-37 (2008).
13
Digital implementation of a BIST method based on binary observations (English)
DSD, 709-713 (2008).
14
Improving the scalability of checkpoint recovery for networks-on-chip (English)
ISCAS, 2793-2796 (2008).
15
Communication aware recovery configurations for networks-on-chip (English)
IOLTS, 201-206 (2008).
16
A case study on phase-locked loop automatic layout generation and transient fault injection analysis (English)
J. Electronic Testing 23, No. 6, 625-633 (2007).
17
Efficient timing closure with a transistor level design flow (English)
VLSI-SoC, 312-315 (2007).
18
io-port 70887990 Rusu, Claudia;
Bougerol, Antonin;
Anghel, Lorena;
Weulersse, Cécile;
Buard, Nadine;
Benhammadi, S.;
Renaud, Nicolas;
Hubert, Guillaume;
Wrobel, Frederic;
Carrière, Thierry;
Gaillard, Rémi
Multiple event transient induced by nuclear reactions in CMOS logic cells (English)
IOLTS, 137-145 (2007).
19
Essential fault-tolerance metrics for noc infrastructures (English)
IOLTS, 37-42 (2007).
20
Result 1 to 20 of 41 total
Start
Contact
Print
General Help
