Result 1 to 20 of 35 total
Comparison of Opamp based and comparator based switched capacitor filter. (English)
Rahaman, Hafizur (ed.) et al., Progress in VLSI design and test. 16th international symposium, VDAT 2012, Shibpur, India, July 1‒4, 2012. Proceedings. Berlin: Springer (ISBN 978-3-642-31493-3/pbk). Lecture Notes in Computer Science 7373, 180-189 (2012).
1
Memory bandwidth and power reduction using lossy reference frame compression in video encoding. (English)
IEEE Trans. Circuits Syst. Video Technol. 21, No. 2, 225-230 (2011).
2
Adaptive keeper design for dynamic logic circuits using rate sensing technique. (English)
IEEE Trans. VLSI Syst. 19, No. 2, 295-304 (2011).
3
Applying genetic algorithms to optimize the power in tiled SNUCA chip multicore architectures (English)
SAC, 1090-1091 (2011).
4
Detection of glycated hemoglobin using 3-aminophenylboronic acid modified graphene oxide (English)
BIODEVICES, 109-113 (2011).
5
A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test (English)
ISCAS, 2035-2038 (2011).
6
A power scalable receiver front-end at 2.4 ghz (English)
ISCAS, 2765-2768 (2011).
7
Voltage and temperature aware statistical leakage analysis framework using artificial neural networks. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29, No. 7, 1056-1069 (2010).
8
False error vulnerability study of on-line soft error detection mechanisms (English)
J. Electronic Testing 26, No. 3, 323-335 (2010).
9
In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits (English)
ISLPED, 259-264 (2010).
10
Accelerating multi-core simulators (English)
SAC, 2377-2382 (2010).
11
Adaptive global elimination algorithm for low power motion estimation (J. Low power electronics 5: 1-16 (2009)). (English)
J. Low Power Electron. 5, No. 2, 255-256 (2009).
12
A workload based lookup table for minimal power operation under supply and body bias control. (English)
J. Low Power Electron. 5, No. 2, 173-184 (2009).
13
Adaptive global elimination algorithm for low power motion estimation. (English)
J. Low Power Electron. 5, No. 1, 1-16 (2009).
14
Latency, power and performance trade-offs in network-on-chips by link microarchitecture exploration (English)
VLSI Design, 163-168 (2009).
15
Voltage and temperature scalable logic cell leakage models considering local variations based on transistor stacks. (English)
J. Low Power Electron. 4, No. 3, 301-319 (2008).
16
Optimal power and noise allocation for analog and digital sections of a low power radio receiver (English)
ISLPED, 271-276 (2008).
17
Power reduction in on-chip interconnection network by serialization (English)
ISLPED, 201-204 (2008).
18
An adaptive, feature-based low power motion estimation algorithm (English)
ICME, 1013-1016 (2008).
19
A 100MHz to 1GHz, 0.35V to 1.5V supply 256 x 64 SRAM block using symmetrized 9T SRAM cell with controlled Read (English)
VLSI Design, 560-565 (2008).
20
Result 1 to 20 of 35 total
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