Result 1 to 20 of 36 total
Throughput analysis for a high-performance FPGA-accelerated real-time search application. (English)
Int. J. Reconfig. Comput. 2012, Article ID 507173, 16 p. (2012).
1
An analytical model of broadcast in QoS-aware wormhole-routed nocs (English)
Journal of Systems and Software 84, No. 1, 12-20 (2011).
2
Performance analysis of on-chip communication structures under device variability (English)
IJERTCS 1, No. 4, 40-62 (2010).
3
An analytical performance model for the spidergon noc with virtual channels (English)
Journal of Systems Architecture - Embedded Systems Design 56, No. 1, 16-26 (2010).
4
Communication modeling of multicast in all-port wormhole-routed nocs (English)
Journal of Systems and Software 83, No. 8, 1327-1336 (2010).
5
Radiation-hardened reconfigurable array with instruction roll-back (English)
Embedded Systems Letters 2, No. 4, 123-126 (2010).
6
A high-level language for programming a noc-based dynamic reconfiguration infrastructure (English)
DASIP, 7-14 (2010).
7
A C++-embedded domain-specific language for programming the MORA soft processor array (English)
ASAP, 141-148 (2010).
8
Search system requirements of patent analysts (English)
SIGIR, 775-776 (2010).
9
An analytical comparison of the Spidergon and rectangular mesh NoCs. (English)
J. Interconnect. Netw. 10, No. 1-2, 167-188 (2009).
10
FPGA-accelerated information retrieval: high-efficiency document filtering (English)
FPL, 417-422 (2009).
11
A low cost reconfigurable soft processor for multimedia applications: design synthesis and programming model (English)
FPL, 534-538 (2009).
12
MAW: A reliable lightweight multi-hop wireless sensor network routing protocol (English)
CSE (2), 487-493 (2009).
13
Programming model and low-level language for a coarse-grained reconfigurable multimedia processor (English)
ERSA, 195-201 (2009).
14
A performance model of multicast communication in wormhole-routed networks on-chip (English)
IPDPS, 1-8 (2009).
15
Design and implementation of the quarc network on-chip (English)
IPDPS, 1-9 (2009).
16
Architectural comparison of instruments for transaction level monitoring of FPGA-based packet processing systems (English)
FCCM, 175-182 (2009).
17
A communication model of broadcast in wormhole-routed networks on-chip (English)
AINA, 315-322 (2009).
18
Quarc: A high-efficiency network on-chip architecture (English)
AINA, 98-105 (2009).
19
Developing energy efficient filtering systems (English)
SIGIR, 664-665 (2009).
20
Result 1 to 20 of 36 total
Start
Contact
Print
General Help
