A 78mW 11.1Gb/s 5-TAP DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS (English)
ISSCC, 368-369 (2009).
1
Bang-bang digital plls at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications (English)
ISSCC, 94-95 (2009).
2
Experimental analysis of substrate noise effect on PLL performance (English)
IEEE Trans. on Circuits and Systems 55-II, No. 7, 638-642 (2008).
3
A direct-conversion receiver integrated circuit for WCDMA mobile systems. (English)
IBM J. Res. Dev. 47, No. 2-3, 337-354 (2003).
4
io-port 05420331 Friedman, Daniel J.;
Meghelli, Mounir;
Parker, Benjamin D.;
Yang, Jungwook;
Ainspan, Herschel A.;
Rylyakov, Alexander V.;
Kwark, Young Hoon;
Ritter, Mark B.;
Shan, Lei;
Zier, Steven J.;
Sorna, Michael;
Soyuer, Mehmet
Sige bicmos integrated circuits for high-speed serial communication links. (English)
IBM J. Res. Dev. 47, No. 2-3, 259-282 (2003).
5
A 1.6-gb/s CMOS phase-frequency locked loop for timing recovery (English)
ISCAS, 187-190 (1995).
6