Result 21 to 36 of 36 total
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring (English)
LCTES, 129-136 (2009).
21
Interface and reconfiguration controller for a wireless MAC-oriented dynamically reconfigurable hardware co-processor (English)
FPL, 591-594 (2008).
22
A formal semantics for control and data flow in the gannet service-based system-on-chip architecture (English)
ERSA, 176-183 (2008).
23
A hardware relaxation paradigm for solving NP-hard problems (English)
BCS Int. Acad. Conf., 75-86 (2008).
24
Quarc: A novel network-on-chip architecture (English)
ICPADS, 705-712 (2008).
25
A performance model of communication in the quarc noc (English)
ICPADS, 908-913 (2008).
26
Modeling differentiated services-based QoS in wormhole-routed nocs (English)
AINA, 942-949 (2008).
27
A type system for static typing of a domain-specific language (English)
FPGA, 258 (2008).
28
A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices (English)
SoCC, 151-154 (2008).
29
Separation of data flow and control flow in reconfigurable multi-core socs using the gannet service-based architecture (English)
AHS, 326-333 (2007).
30
Implementation of finite state machines on a reconfigurable device (English)
AHS, 386-396 (2007).
31
Analytical modelling of communication in the rectangular mesh noc (English)
ICPADS, 1-8 (2007).
32
Communication modelling of the spidergon noc with virtual channels (English)
ICPP, 76 (2007).
33
An analytical performance model for the spidergon noc (English)
AINA, 1014-1021 (2007).
34
The gannet service-based soc: A service-level reconfigurable architecture (English)
AHS, 255-261 (2006).
35
A compact test structure for characterisation of leakage currents in sub-micron CMOS technologies (English)
Microelectronics Reliability 41, No. 12, 1939-1945 (2001).
36
Result 21 to 36 of 36 total
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