Result 1 to 12 of 12 total
Transistor sizing of custom high-performance digital circuits with parametric yield considerations (English)
DAC, 781-786 (2010).
1
First-order incremental block-based statistical timing analysis. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 25, No. 10, 2170-2180 (2006).
2
Formal verification - prove it or pitch it (English)
DAC, 710-711 (2003).
4
Design methodology for the high-performance G4 S/390 (English)
ICCD, 232-240 (1997).
8
The EVE companion simulator (English)
EURO-DAC, 290-295 (1990).
9
SLS-a fast switch-level simulator [for MOS]. (English)
IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 7, No. 8, 838-849 (1988).
10
The IBM engineering verification engine (English)
DAC, 218-224 (1988).
11
SLS - a fast switch level simulator for verification and fault coverage analysis (English)
DAC, 164-170 (1986).
12
Result 1 to 12 of 12 total